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CY24242OXCT PDF预览

CY24242OXCT

更新时间: 2024-11-21 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
10页 220K
描述
Laser Printer System Frequency Synthesizer

CY24242OXCT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:5.30 MM, LEAD FREE, SSOP-28针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.75
Is Samacsys:N其他特性:ALSO REQUIRES 2.5V SUPPLY
JESD-30 代码:R-PDSO-G28JESD-609代码:e4
长度:10.2 mm湿度敏感等级:3
端子数量:28最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133.3 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2 mm
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:5.3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CY24242OXCT 数据手册

 浏览型号CY24242OXCT的Datasheet PDF文件第2页浏览型号CY24242OXCT的Datasheet PDF文件第3页浏览型号CY24242OXCT的Datasheet PDF文件第4页浏览型号CY24242OXCT的Datasheet PDF文件第5页浏览型号CY24242OXCT的Datasheet PDF文件第6页浏览型号CY24242OXCT的Datasheet PDF文件第7页 
CY24242  
Laser Printer System Frequency Synthesizer  
Table 1. Pin Selectable Frequency[1]  
Features  
CPU(0:3),  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum technology  
FS1 FS0  
SDRAM(0:3)  
133.3 MHz  
100 MHz  
USBCLK  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
0
0
1
1
0
1
0
1
• Reduces measured EMI by as much as 10 dB  
• Four skew-controlled copies of CPU output  
• Four skew-controlled copies of SDRAM output  
• One copy of 14.31818-MHz Reference output  
• One copy of 48-MHz USB clock (not spread)  
• Selectable SSFTG modulation width  
66.6 MHz  
50 MHz  
Table 2. Spread Characteristics.  
CPU(0:3),  
SDRAM(0:3)  
• Available in 28-pin SSOP (209 mil)  
SSON#  
SS%1  
SS%0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
–0.5%  
–1.0%  
–2.5%  
–3.75%  
0 (off)\  
0 (off)  
0 (off)  
0 (off)  
Key Specifications  
Supply Voltage:  
VDDCORE: ........................................................... 3.3V±10%  
VDDC: ............................................... 3.3V±10% or 2.5V±5%  
VDDS: ............................................... 3.3V±10% or 2.5V±5%  
VDDU: ............................................... 3.3V±10% or 2.5V±5%  
CPU Clock Cycle to Cycle Jitter: ................................250ps  
USBCLK Long term Jitter:....................................... ± 500 ps  
CPU0:3 Clock Skew: ..................................................250ps  
CPU, SDRAM Output on Resistance: .............................15  
Logic inputs have 250K-ohm pull-up resistors  
Pin Configuration[2, 3]  
Block Diagram  
REF  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
USBCLKEN  
GND  
VDDCORE  
REF  
X1  
X2  
XTAL  
OSC  
2
GND  
3
USBCLK  
VDDU  
4
X1  
X2  
PLL Ref Freq  
5
CPU0  
SDRAM3  
SDRAM2  
VDDS  
6
CPU1  
7
VDDC  
SSON#  
8
CPU2  
CPU3  
GND  
9
SDRAM1  
SDRAM0  
GND  
10  
11  
12  
13  
14  
SS%1  
SS%0  
SS%1*  
SSON#^  
FS1*  
VDDCORE  
*SDEN  
*SS%0  
CPU0:3  
FS0*  
SDRAM0:3  
PLL 1  
FS0  
FS1  
SDEN  
USBCLKEN  
PLL 2  
USBCLK  
Notes:  
1. All clock output loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.  
2. Signals marked with [*] have internal pull-up resistors  
3. Signal marked with[^] has internal pull-down resistors.  
Cypress Semiconductor Corporation  
Document #: 38-07268 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised January 19, 2005  

CY24242OXCT 替代型号

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