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CY24272ZXC PDF预览

CY24272ZXC

更新时间: 2024-11-21 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
13页 343K
描述
Rambus㈢ XDR⑩ Clock Generator with Zero SDA Hold Time

CY24272ZXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.77系列:24272
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G28
JESD-609代码:e4长度:9.7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:28实输出次数:4
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.015 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

CY24272ZXC 数据手册

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CY24272  
Rambus® XDR™ Clock Generator with  
Zero SDA Hold Time  
Features  
Table 1. Device Comparison  
Meets Rambus® Extended Data Rate (XDR™) clocking  
requirements  
CY24271  
CY24272  
SDA hold time = 300 ns  
(SMBus compliant)  
SDA hold time = 0 ns  
(I2C compliant)  
25 ps typical cycle-to-cycle jitter  
–135 dBc/Hz typical phase noise at 20 MHz offset  
R
RC = 200Ω typical  
RRC = 295Ω minimum  
(Reduced output drive)  
100 or 133 MHz differential clock input  
300–667 MHz high speed clock support  
Quad (open drain) differential output drivers  
Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4  
Spread Aware™  
(Rambus standard drive)  
2.5V operation  
28-pin TSSOP package  
Logic Block Diagram  
/BYPASS  
EN  
EN  
RegA  
CLK0  
CLK0B  
EN  
RegB  
CLK1  
Bypass  
MUX  
CLK1B  
EN  
RegC  
PLL  
REFCLK,REFCLKB  
CLK2  
CLK2B  
EN  
RegD  
CLK3  
CLK3B  
SCL  
SDA  
ID0  
ID1  
Cypress Semiconductor Corporation  
Document Number: 001-42414 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 9, 2007  
[+] Feedback  

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