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CY245ZXC-XXXT PDF预览

CY245ZXC-XXXT

更新时间: 2024-11-23 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路石英晶振压控振荡器光电二极管
页数 文件大小 规格书
9页 164K
描述
Factory Programmable Quad PLL Clock Generator with VCXO

CY245ZXC-XXXT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, LEAD FREE, MO-153, TSSOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:NJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
湿度敏感等级:3端子数量:20
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:166 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:100 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY245ZXC-XXXT 数据手册

 浏览型号CY245ZXC-XXXT的Datasheet PDF文件第2页浏览型号CY245ZXC-XXXT的Datasheet PDF文件第3页浏览型号CY245ZXC-XXXT的Datasheet PDF文件第4页浏览型号CY245ZXC-XXXT的Datasheet PDF文件第5页浏览型号CY245ZXC-XXXT的Datasheet PDF文件第6页浏览型号CY245ZXC-XXXT的Datasheet PDF文件第7页 
CY244/45ZXC  
Factory Programmable Quad PLL Clock Generator with VCXO  
Features  
Benefits  
• Fully integrated phase-locked loops (PLLs)  
• Selectable Output Frequency  
• Programmable Output Frequencies  
• Output Frequency Range of 5–166 MHz  
• Input Frequency Range  
— Crystal: 10–30 MHz  
— External Reference: 1–100 MHz  
• Analog VCXO  
• Meets most Digital Set Top Box, DVD Recorder and DTV  
application requirements  
• Multiple high-performance PLLs allow synthesis of  
unrelated frequencies  
• Integration eliminates the need for external loop filter  
components  
• Meets critical timing requirements in complex system  
designs  
• Enables application compatibility  
• Complete VCXO solution with ±120 ppm (minimum pull  
• 16-/20-pin TSSOP packages  
• 3.3V operation  
range)  
Block Diagram  
CLKA  
CLKB  
CLKC  
PLL1  
PLL2  
PLL3  
PLL4  
XIN  
VCXO  
XOUT  
CLKD  
Divider  
&
Multiplexer  
VIN  
CLKE  
CLKF  
CLKG  
FS0/1/2  
Select  
Logic  
Pin Configuration OE  
20-Pin TSSOP  
16-Pin TSSOP  
XIN  
FS2  
1
2
3
4
5
6
7
20  
19  
18  
17  
16  
XOUT  
VDD  
XIN  
AVDD  
VIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
XOUT  
AVDD  
VIN  
CLKG  
CLKF  
VSS  
VDD  
CLKG  
CLKF  
VSS  
AVSS  
OE/PD  
AVSS  
CLKA/OE  
VSS  
CY245ZXC  
CY244ZXC  
15  
14  
CLKE  
12  
11  
10  
9
CLKA  
VSS  
CLKD  
VDD  
FS0  
VDD  
8
9
13  
12  
CLKB  
FS1  
FS0  
CLKB  
FS1  
CLKC  
10  
11  
CLKC  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07748 Rev. **  
Revised March 7, 2005  

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