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CY24212SC-5T

更新时间： 2024-11-20 22:50:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器石英晶振压控振荡器
页数	文件大小	规格书
6页	114K
描述
MediaClock MPEG Clock Generator with VCXO

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中文翻译

获取价格

数据手册

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CY24212SC-5T 数据手册

CY24212

PRELIMINARY

MediaClock™

MPEG Clock Generator with VCXO

Features

• Integrated phase-locked loop (PLL)

• Low jitter, high-accuracy outputs

• VCXO with analog adjust

• 3.3V operation

Benefits

Highest-performance PLL tailored for multimedia applications

Meets critical timing requirements in complex system designs

Large ±150-ppm range, better linearity

Enables application compatibility

Part Number Outputs

Input Frequency Range

13.5 MHz/27 MHz (selectable)

Output Frequencies

CY24212-1

CY24212-2

CY24212-3

CY24212-5

27 MHz

13.5 MHz/27 MHz (selectable)

Two copies of 27 MHz

27 MHz/27.027 MHz (-1 ppm)

27 MHz/27.027 MHz (0 ppm)

27 MHz

Logic Block Diagram

OUTPUT

DIVIDERS

XIN

OSC

CLKA (27 MHz)

XOUT

VCO

27 MHz (-2)

27/27.027 MHz (-3)

VCXO

FSEL

PLL

VSS

VDD

Pin Configurations

CY24212-3,-5

8-pin SOIC

CY24212-1

8-pin SOIC

CY24212-2

8-pin SOIC

XOUT

VSS

XOUT

XIN

CLKB (27/27.027 MHz)

VDD

VCXO

VSS

CLKB 27 MHz

VDD

VCXO

VSS

VDD

VCXO

VSS

FSEL

CLKA 27 MHz

Table 1. CY24212 (-1, -2) Frequency Select Option

FSEL

Reference

13.5 MHz

27 MHz

CLKA/CLKB

27 MHz

Table 2. CY24212 (-3, -5) Frequency Select Option

FSEL

Reference

27 MHz

CLKA

27 MHz

CLKB

27 MHz

27.027 MHz

Cypress Semiconductor Corporation

Document #: 38-07402 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised February 18, 2003

12 3 4 5 6

中文翻译

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与CY24212SC-5T相关器件

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