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CY24210-6 PDF预览

CY24210-6

更新时间: 2024-11-22 07:43:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管
页数 文件大小 规格书
5页 86K
描述
Clock Generator, PDSO8,

CY24210-6 数据手册

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CY24210  
100-MHz Clock Generator with Spread Spectrum  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• Spread Spectrum  
High-performance PLL tailored for multimedia applications  
Meets critical timing requirements in complex system designs  
Spread Spectrum outputs for EMI reduction  
Enables application compatibility  
• 3.3V operation  
Part Number Outputs  
CY24210  
Input Frequency Range  
Output Frequencies  
3
14.31818 MHz  
Two copies of 100 MHz, 14.31818 MHz  
Logic Block Diagram  
REF  
XIN  
OSC  
Q
Φ
CLK2  
CLK1  
OUTPUT  
DIVIDERS  
SPREAD  
SPECTRUM  
XOUT  
VCO  
P
PLL  
SSON  
VSS  
VDD  
Spread Spectrum Profiles  
Pin Configurations  
Part Numbers  
CY24210SC-3  
CY24210SC-4  
CY24210SC-5  
CY24210SC-6  
CY24210SC-7  
Center Spread Percentage  
+ 1.875%  
CY24210  
8-pin SOIC  
+ 1.375%  
+ 2.375%  
XOUT  
1
2
3
4
8
7
6
5
XIN  
CLK1  
CLK2  
VDD  
SSON  
VSS  
+ 2.875%  
+ 3.375%  
REF  
Pin Description  
Pin Name  
XIN  
Pin Number  
Description  
1
Reference Crystal Input  
Voltage Supply  
VDD  
2
3
4
5
6
7
8
SSON  
VSS  
Spread Spectrum Control for CLK1, CLK2, 0 = SS off, 1 = SS on, Internal Pull-up Resistor  
Ground  
REF  
Buffered Reference Clock Output  
CLK2  
CLK1  
100-MHz Clock Output with Spread Spectrum  
100-MHz Clock Output with Spread Spectrum  
Reference Crystal Output  
[1]  
XOUT  
Note:  
1. Float XOUT if XIN is externally driven.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07361 Rev. **  
Revised March 27, 2002  

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