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CY24204KZXC-3 PDF预览

CY24204KZXC-3

更新时间: 2024-11-27 14:49:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 229K
描述
Video Clock Generator, 74.25MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16

CY24204KZXC-3 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, LEAD FREE, MO-153, TSSOP-16
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.76Is Samacsys:N
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm湿度敏感等级:3
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:74.25 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3.3 V
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大压摆率:25 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

CY24204KZXC-3 数据手册

 浏览型号CY24204KZXC-3的Datasheet PDF文件第2页浏览型号CY24204KZXC-3的Datasheet PDF文件第3页浏览型号CY24204KZXC-3的Datasheet PDF文件第4页浏览型号CY24204KZXC-3的Datasheet PDF文件第5页浏览型号CY24204KZXC-3的Datasheet PDF文件第6页浏览型号CY24204KZXC-3的Datasheet PDF文件第7页 
CY24204  
MediaClock™  
DTV, STB Clock Generator  
Features  
Benefits  
Integrated phase-locked loop (PLL)  
Low jitter, high-accuracy outputs  
VCXO with Analog Adjust  
3.3V operation  
Internal PLL with up to 400-MHz internal operation  
Meets critical timing requirements in complex system designs  
Large ±150-ppm range, better linearity  
Enables application compatibility  
Part Number Outputs  
Input Frequency  
27-MHz Crystal Input  
Output Frequency Range  
CY24204-3  
4
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable)  
CY24204-4  
4
27-MHz Crystal Input  
27-MHz Crystal Input  
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable,  
Increased VCXO pull range)  
CY24204-5  
4
Two copies of 27-MHz reference clock output, two copies of  
27/27.027/74.250/74.17582418 MHz (frequency selectable,  
Increased output drive strength)  
Logic Block Diagram  
XIN  
Q
OSC.  
Φ
VCO  
OUTPUT  
XOUT  
VCXO  
MULTIPLEXER  
CLK1  
AND  
P
DIVIDERS  
CLK2  
PLL  
REFCLK1  
REFCLK2  
(-3,-4,-5)  
FS0  
FS1  
OE  
VSSL  
VSS  
VDD  
AVDD AVSS  
VDDL  
Cypress Semiconductor Corporation  
Document #: 38-07450 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 22, 2008  
[+] Feedback  

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