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CY241V8ASXC-11 PDF预览

CY241V8ASXC-11

更新时间: 2024-11-28 01:16:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 481K
描述
Integrated phase locked loop (PLL)

CY241V8ASXC-11 数据手册

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CY241V8A-11  
MPEG Clock Generator with VCXO  
MPEG Clock Generator with VCXO  
Features  
Benefits  
Integrated phase locked loop (PLL)  
Low jitter, high accuracy outputs  
VCXO with analog adjust  
3.3 V operation  
Highest performance PLL tailored for multimedia applications  
Meets critical timing requirements in complex system designs  
Application compatibility for a wide variety of designs  
Frequency Table  
VCXO Control  
Part Number Outputs  
Input Frequency Range  
Output Frequencies  
Other Features  
Curve  
CY241V8A-11  
1
13.5 MHz pullable crystal input One copy of 54 MHz  
per Cypress specification  
linear  
Pinout-compatible with CY2411  
Block Diagram  
13.5 XIN  
XOUT  
Output  
Divider  
OSC  
PLL  
54 MHz  
VDD  
VSS  
VCXO  
Pin Configuration  
Figure 1. 8-pin SOIC pinout  
Pin Descriptions  
Name  
XIN  
Pin Number  
Description  
1
2, 5  
3
Reference crystal input  
Voltage supply  
VDD  
VCXO  
VSS  
Input analog control for VCXO  
Ground  
4, 7  
6
54 MHz  
XOUT  
54 MHz clock output  
Reference crystal output  
8
Cypress Semiconductor Corporation  
Document Number: 38-07654 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 21, 2012  

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