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CY241V08A-41 PDF预览

CY241V08A-41

更新时间: 2024-11-27 09:41:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器微控制器和处理器石英晶振压控振荡器光电二极管
页数 文件大小 规格书
6页 122K
描述
MPEG Clock Generator with VCXO

CY241V08A-41 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:NJESD-30 代码:R-PDSO-G8
JESD-609代码:e0湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):220电源:3.3 V
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:40 mA标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
Base Number Matches:1

CY241V08A-41 数据手册

 浏览型号CY241V08A-41的Datasheet PDF文件第2页浏览型号CY241V08A-41的Datasheet PDF文件第3页浏览型号CY241V08A-41的Datasheet PDF文件第4页浏览型号CY241V08A-41的Datasheet PDF文件第5页浏览型号CY241V08A-41的Datasheet PDF文件第6页 
CY241V08A-41  
MPEG Clock Generator with VCXO  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• VCXO with analog adjust  
• 3.3V operation  
• Highest-performance PLL tailored for multimedia applica-  
tions  
• Meets critical timing requirements in complex system  
designs  
• Application compatibility for a wide variety of designs  
Frequency Table  
VCXOControl  
Part Number Outputs Input Frequency Range  
Output Frequencies  
Curve  
Other Features  
CY241V08A-41  
1
27-MHz pullable crystal input One copy of 27 MHz linear  
Pinout-compatible with  
per Cypress specification  
One copy of 83.33 MHz  
(non-pullable)  
MK3741  
Block Diagram  
OUTPUT  
DIVIDER  
PLL  
83.33MHz  
54 REF  
27 XIN  
XOUT  
XBUF/27MHz  
OSC  
VCXO  
VSS  
VDD  
Pin Configuration  
CY241V08A-41  
8-pin SOIC  
XOUT  
1
2
3
4
8
7
6
5
XIN  
REF  
83.33 MHz  
VDD  
VCXO  
VSS  
XBUF/27 MHz  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07655 Rev. *A  
Revised April 22, 2004  

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