Datasheet > CY241V08-11

CY241V08-11

更新时间： 2022-01-19 01:08:00

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
6页	43K
描述
Clocks and Buffers

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数据手册

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CY241V08-11 数据手册

PRELIMINARY

CY241V08-11

MPEG Clock Generator with VCXO

Features

Benefits

• Integrated phase-locked loop (PLL)

• Low-jitter, high-accuracy outputs

• VCXO with analog adjust

• 3.3V operation

• Highest-performance PLL tailored for multimedia applica-

tions

• Meets critical timing requirements in complex system

designs

• Application compatibility for a wide variety of designs

Frequency Table

Output

VCXOControl

Curve

Part Number Outputs

CY241V08-11

Input Frequency Range

Frequencies

Other Features

13.5-MHz pullable crystal input One copy of 27 MHz linear

per Cypress specification

Pinout compatible with CY2411

Block Diagram

OUTPUT

DIVIDER

13.5 XIN

XOUT

PLL

OSC

54MHz

VCXO

VSS

VDD

Pin Configuration

CY241V08-11

8-pin SOIC

XOUT

XIN

VSS

VDD

VCXO

VSS

54MHz

VDD

Cypress Semiconductor Corporation

Document #: 38-07571 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised September 8, 2003

12 3 4 5 6

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