Datasheet > CY241V08A-01

CY241V08A-01

更新时间： 2024-02-25 03:24:13

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器石英晶振压控振荡器
页数	文件大小	规格书
6页	68K
描述
MPEG Clock Generator with VCXO

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中文翻译

获取价格

数据手册

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CY241V08A-01 数据手册

CY241V08A-01,04

CY241V8A-01

MPEG Clock Generator with VCXO

Features

Benefits

• Integrated phase-locked loop (PLL)

• Low-jitter, high-accuracy outputs

• VCXO with analog adjust

• Digital VCXO control

• Second source for existing designs

• Highest-performance PLL tailored for multimedia applica-

tions

• 3.3V operation

• Meets critical timing requirements in complex system

designs

• Compatible with MK3727 (–1, –4)

• Application compatibility for a wide variety of designs

• Enables design compatibility

•

• Lower drive strength settings (CY241V08A–04)

CY241V08A-01,-04 Logic Block Diagram

13.5 XIN

OUTPUT

DIVIDERS

OSC

27 MHz

XOUT

VCO

PLL

VCXO

VSS

VDD

Pin Configurations

CY241V08A-01,-04

8-pin SOIC

XOUT

XIN

NC or VSS

NC or VDD

27 MHz

VDD

VCXO

VSS

Part

Number

Output

Frequencies

VCXOControl

Curve

Outputs

Input Frequency Range

Other Features

CY241V08A-01

13.5-MHz pullable crystal input per 1 copy of 27 MHz linear

Cypress specification

Compatible with MK3727

CY241V08A-04

13.5-MHz pullable crystal input per 1 copy of 27 MHz linear

Cypress specification

Same as CY241V08A-01

except lower drive

strength settings

Cypress Semiconductor Corporation

Document #: 38-07656 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 14, 2005

12 3 4 5 6

中文翻译

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