Datasheet > CY241V08A-06

CY241V08A-06

更新时间： 2024-11-23 21:53:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器石英晶振压控振荡器
页数	文件大小	规格书
6页	124K
描述
MPEG Clock Generator with VCXO

阅读下载

中文翻译

获取价格

数据手册

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CY241V08A-06 数据手册

CY241V08A-05,06

MPEG Clock Generator with VCXO

Features

Benefits

• Integrated phase-locked loop (PLL)

• Low-jitter, high-accuracy outputs

• VCXO with analog adjust

• 3.3V operation

• Compatible with MK3727 (–5, –6)

• Application compatibility for a wide variety of designs

• Enables design compatibility

• Lower drive strength settings (CY241V08A–06)

• Digital VCXO control

• Electromagnetic interference (EMI) reduction for standards

compliance

• Second source for existing designs

• Highest-performance PLL tailored for multimedia applica-

tions

• Meets critical timing requirements in complex system

designs

CY241V08A–05,–06 Logic Block Diagram

13.5 XIN

OUTPUT

DIVIDERS

OSC

27 MHz

XOUT

VCXO

VCO

PLL

VSS

VDD

Pin Configurations

CY241V08A–05,–06

8-pin SOIC

XOUT

XIN

NC or VSS

NC or VDD

VDD

VCXO

VSS

27 MHz

Part

Output

VCXOControl

Curve

Number

Outputs

Input Frequency Range

Frequencies

Other Features

CY241V08A–05

13.5-MHz pullable crystal input per 1 copy of 27 MHz non-linear

Compatible with

Cypress specification

MK3727A non linear

VCXO control

CY241V08A–06

13.5-MHz pullable crystal input per 1 copy of 27 MHz non-linear

Cypress specification

Same as CY241V08A–05

except lower drive

strength

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07670 Rev. **

Revised April 09, 2004

12 3 4 5 6

中文翻译

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