Datasheet > CY241V08-41

CY241V08-41

更新时间： 2022-01-19 01:08:00

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
6页	45K
描述
Clocks and Buffers

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数据手册

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CY241V08-41 数据手册

PRELIMINARY

CY241V08-41

MPEG Clock Generator with VCXO

Features

Benefits

• Integrated phase-locked loop (PLL)

• Low-jitter, high-accuracy outputs

• VCXO with analog adjust

• 3.3V operation

• Highest-performance PLL tailored for multimedia applica-

tions

• Meets critical timing requirements in complex system

designs

• Application compatibility for a wide variety of designs

Frequency Table

VCXOControl

Part Number Outputs Input Frequency Range

Output Frequencies

Curve

Other Features

CY241V08-41

27-MHz pullable crystal input One copy of 27MHz

linear

Pinout compatible with MK3741

per Cypress specification

One copy of 83.33MHz

(non-pullable)

Block Diagram

OUTPUT

DIVIDER

PLL

54 REF

83.33MHz

27 XIN

XOUT

OSC

XBUF/27MHz

VCXO

VSS

VDD

Pin Configuration

CY241V08-41

8-pin SOIC

XOUT

XIN

REF

VDD

VCXO

VSS

83.33 MHz

XBUF/27 MHz

Cypress Semiconductor Corporation

Document #: 38-07570 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised September 8, 2003

12 3 4 5 6

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