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CY24142ZC-01T PDF预览

CY24142ZC-01T

更新时间: 2024-11-23 22:07:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
7页 130K
描述
MediaClock Multimedia Clock Generator

CY24142ZC-01T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 MM, MO-153, TSSOP-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
端子数量:16最高工作温度:85 °C
最低工作温度:最大输出时钟频率:54 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.45 V主时钟/晶体标称频率:18.432 MHz
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Clock Generators最大压摆率:25 mA
最大供电电压:3.6 V最小供电电压:3.15 V
标称供电电压:3.45 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

CY24142ZC-01T 数据手册

 浏览型号CY24142ZC-01T的Datasheet PDF文件第2页浏览型号CY24142ZC-01T的Datasheet PDF文件第3页浏览型号CY24142ZC-01T的Datasheet PDF文件第4页浏览型号CY24142ZC-01T的Datasheet PDF文件第5页浏览型号CY24142ZC-01T的Datasheet PDF文件第6页浏览型号CY24142ZC-01T的Datasheet PDF文件第7页 
CY24142  
MediaClock™  
Multimedia Clock Generator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• 3.3V operation  
• Integrated high-performance PLL eliminates the need for  
— external loop filter components  
• Meets critical timing requirements in complex system  
designs  
• Enables application compatibility  
Logic Block Diagram  
XIN  
Q
OSC.  
Φ
VCO  
OUTPUT  
XOUT  
MULTIPLEXER  
CLK1 13.5 MHz  
CLK2 54 MHz  
AND  
P
DIVIDERS  
PLL  
CLK3 18.432 MHz  
CLK4 18.432 MHz  
OE1  
OE2  
VSS  
AVDD AVSS  
VDDL  
VDD  
VSSL  
Pin Configuration  
CY24142  
16-pin TSSOP  
XOUT  
1
2
3
4
5
6
16  
15  
14  
13  
12  
XIN  
VDD  
AVDD  
CLK4  
CLK3  
VSS  
OE1  
AVSS  
VSSL  
NC  
NC  
VDDL  
11  
10  
7
8
OE2  
CLK2  
9
CLK1  
Frequency Table  
Part Number Outputs  
Input Frequency  
Output Frequency Range  
13.5 MHz, 54 MHz, 2 x 18.432 MHz  
CY24142-01  
4
18.432  
Output Enable Options[1]  
OE2  
OE1  
CLK1  
13.5  
13.5  
13.5  
13.5  
CLK2  
OFF  
54  
OFF  
54  
CLK3  
OFF  
18.432  
OFF  
CLK4  
OFF  
OFF  
18.432  
18.432  
Unit  
MHz  
MHz  
MHz  
MHz  
0
0
1
1
0
1
0
1
18.432  
Note:  
1. Output driven LOW when “OFF.”  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07532 Rev. *B  
Revised January 19, 2005  

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