Datasheet > CY24130-1

CY24130-1

更新时间： 2022-12-01 16:22:08

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
5页	128K
描述
HOTLink SMPTE Receiver Training Clock

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数据手册

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CY24130-1 数据手册

CY24130

HOTLink II™ SMPTE Receiver Training Clock

Features

Benefits

• Integrated phase-locked loop

• Low-jitter, high-accuracy outputs

• 3.3V operation

• Internal PLL with up to 400-MHz internal operation

• Meets critical timing requirements in complex system

designs

• Enables application compatibility

Part Number Outputs

Input Frequency

Output Frequency Range

CY24130-1

27 MHz (Driven Reference) 1 copy 27-MHz reference clock output

1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)

CY24130-2

27 MHz (Crystal Reference) 1 copy 27-MHz reference clock output

1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)

Logic Block Diagram

XIN

XOUT

OSC.

VCO

PLL

OUTPUT

MULTIPLEXER

AND

CLKA

DIVIDERS

REFCLK

VSS

AVDD AVSS

VDDL VDD

VSSL

Pin Configuration

CY24130-1, -2

16-pin TSSOP

XOUT

XIN

VDD

AVDD

AVSS

VSSL

REFCLK

VSS

N/C

VDDL

N/C

CLKA

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07711 Rev. **

Revised February 04, 2005

12 3 4 5

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