Datasheet > CY2302

CY2302

更新时间： 2024-11-28 22:10:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		倍频器
页数	文件大小	规格书
7页	106K
描述
Frequency Multiplier and Zero Delay Buffer

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CY2302 数据手册

CY2302

Frequency Multiplier and Zero Delay Buffer

Features

Table 1. Configuration Options

• Two outputs

FBIN

OUT1

OUT2

FS0

FS1

OUT1

2 X REF

4 X REF

REF

OUT2

REF

• Configuration options allow various multiplications of

the reference frequency—refer to Table 1 to determine

the specific option which meets your multiplication

needs

2 X REF

REF/2

• Available in 8-pin SOIC package

8 X REF

4 X REF

8 X REF

2 X REF

16 X REF

4 X REF

2 X REF

4 X REF

REF

Key Specifications

Operating Voltage: ............................3.3V ±5% or 5.0 ±10%

Operating Range: ......................10 MHz < f_OUT1< 133 MHz

Absolute Jitter: ......................................................... ±500 ps

Output to Output Skew: ............................................. 250 ps

8 X REF

Propagation Delay: ................................................... ±350 ps

Propagation delay is affected by input rise time.

Block Diagram

Pin Configuration

SOIC

External feedback connection to

OUT1 or OUT2, not both

FBIN

OUT2

VDD

OUT1

FS1

GND

FS0

÷Q

FS1

Phase

Detector

Charge

Pump

Reference

Input

Loop

Filter

Output

Buffer

OUT1

OUT2

VCO

Output

Buffer

÷2

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07154 Rev. **

Revised September 25, 2001

12 3 4 5 6 7

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