Datasheet > CY2303_12

CY2303_12

更新时间： 2024-11-26 12:50:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	350K
描述
Phase-Aligned Clock Multiplier

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数据手册

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CY2303_12 数据手册

CY2303

Phase-Aligned Clock Multiplier

Features

Functional Description

■ 3-Multiplier configuration (1x, 2x, 4x ref)

The CY2303 is a 3 output 3.3 V phase-aligned system clock

designed to distribute high-speed clocks in PC, workstation,

datacom, telecom, and other high-performance applications.

■ 10MHzto166.67MHzoperatingrange(referenceinputfrom

10 MHz to 41.67 MHz)

The part allows user to obtain 1x, 2x, and 4x REFIN output

frequencies on respective output pins.

■ Phase alignment

■ 80 ps typical period jitter

■ Output enable pin

The CY2303 has an on-chip PLL, which locks to an input clock

presented on the REFIN pin. The PLL feedback is internally

connected to the REF output. The input-to-output is

guaranteed to be less than 200 ps, and output-to-output skew

is guaranteed to be less than 200 ps.

■ 3.3 V operation

■ 5 V tolerant input

Multiple CY2303 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 400 ps.

■ 8-pin 150-mil small-outline integrated circuit (SOIC) package

■ Commercial temperature range

Logic Block Diagram

FBK

REF

PLL

REFIN

REFx2

REFx4

Cypress Semiconductor Corporation

Document #: 38-07249 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 01, 2010

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