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CY2302SXI-1T PDF预览

CY2302SXI-1T

更新时间: 2024-11-23 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 逻辑集成电路光电二极管倍频器驱动
页数 文件大小 规格书
7页 85K
描述
Frequency Multiplier and Zero Delay Buffer

CY2302SXI-1T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:1 week
风险等级:1.57其他特性:IT ALSO OPERATES WITH 5V SUPPLY
系列:23S输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.889 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3/5 VProp。Delay @ Nom-Sup:0.35 ns
传播延迟(tpd):0.35 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.727 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.8985 mm
最小 fmax:133 MHzBase Number Matches:1

CY2302SXI-1T 数据手册

 浏览型号CY2302SXI-1T的Datasheet PDF文件第2页浏览型号CY2302SXI-1T的Datasheet PDF文件第3页浏览型号CY2302SXI-1T的Datasheet PDF文件第4页浏览型号CY2302SXI-1T的Datasheet PDF文件第5页浏览型号CY2302SXI-1T的Datasheet PDF文件第6页浏览型号CY2302SXI-1T的Datasheet PDF文件第7页 
CY2302  
Frequency Multiplier and Zero Delay Buffer  
Features  
Table 1. Configuration Options  
• 90ps typical jitter OUT2  
FBIN  
OUT1  
OUT1  
OUT1  
OUT1  
OUT2  
OUT2  
OUT2  
OUT2  
FS0  
0
FS1  
0
OUT1  
2 X REF  
4 X REF  
REF  
OUT2  
REF  
• 200ps typical jitter OUT1  
• 65ps typical output-to-output skew  
• 90ps typical propagation delay  
• Voltage range: 3.3V±5%, or 5V±10%  
• Output frequency range: 5MHz-133MHz  
• Two outputs  
1
0
2 X REF  
REF/2  
0
1
1
1
8 X REF  
4 X REF  
8 X REF  
2 X REF  
16 X REF  
4 X REF  
2 X REF  
4 X REF  
REF  
0
0
1
0
• Configuration options allow various multiplications of  
the reference frequency—refer to Table 1 to determine  
the specific option which meets your multiplication  
needs  
0
1
1
1
8 X REF  
• Available in 8-pin SOIC package  
Block Diagram  
Pin Configuration  
SOIC  
External feedback connection to  
OUT1 or OUT2, not both  
FBIN  
FBIN  
IN  
1
2
3
4
8
7
6
5
OUT2  
VDD  
OUT1  
FS1  
GND  
FS0  
FS0  
÷Q  
FS1  
Phase  
Detector  
Charge  
Pump  
IN  
Reference  
Input  
Loop  
Filter  
Output  
Buffer  
OUT1  
OUT2  
VCO  
Output  
Buffer  
÷2  
Cypress Semiconductor Corporation  
Document #: 38-07154 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised August 29, 2005  

CY2302SXI-1T 替代型号

型号 品牌 替代类型 描述 数据表
CY2302SXI-1 CYPRESS

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Frequency Multiplier and Zero Delay Buffer
CY2302SXC-1 CYPRESS

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Frequency Multiplier and Zero Delay Buffer

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