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CY2303SXC PDF预览

CY2303SXC

更新时间: 2024-11-24 14:56:47
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
14页 398K
描述
3.3V Zero Delay Buffer

CY2303SXC 数据手册

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CY2303  
Phase-Aligned Clock Multiplier  
Phase-Aligned Clock Multiplier  
Features  
Functional Description  
3-Multiplier configuration (1×, 2×, 4× ref)  
The CY2303 is a 3 output 3.3 V phase-aligned system clock  
designed to distribute high-speed clocks in PC, workstation,  
datacom, telecom, and other high-performance applications.  
10 MHz to 166.67 MHz operating range (reference input from  
10 MHz to 41.67 MHz)  
The part allows user to obtain 1×, 2×, and 4× REFIN output  
frequencies on respective output pins.  
Phase alignment  
80 ps typical period jitter  
Output enable pin  
The CY2303 has an on-chip PLL, which locks to an input clock  
presented on the REFIN pin. The PLL feedback is internally  
connected to the REF output. The input-to-output is guaranteed  
to be less than 200 ps, and output-to-output skew is guaranteed  
to be less than 200 ps.  
3.3 V operation  
5 V tolerant input  
Multiple CY2303 devices can accept the same input clock and  
distribute it in a system. In this case, the skew between the  
outputs of two devices is guaranteed to be less than 400 ps.  
8-pin 150-mil small-outline integrated circuit (SOIC) package  
Commercial temperature range  
For a complete list of related documentation, click here.  
Logic Block Diagram  
FBK  
x1  
REF  
PLL  
REFIN  
x2  
REFx2  
x4  
REFx4  
OE  
Cypress Semiconductor Corporation  
Document Number: 38-07249 Rev. *K  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 24, 2018  

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