Datasheet > CY2304-2

CY2304-2

更新时间： 2024-11-25 22:10:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
8页	112K
描述
3.3V Zero Delay Buffer

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CY2304-2 数据手册

CY2304

3.3V Zero Delay Buffer

The part has an on-chip phase-locked loop (PLL) that locks to

an input clock presented on the REF pin. The PLL feedback is

required to be driven into the FBK pin, and can be obtained

from one of the outputs. The input-to-output skew is

guaranteed to be less than 250 ps, and output-to-output skew

is guaranteed to be less than 200 ps.

Features

• Zero input-output propagation delay, adjustable by

capacitive load on FBK input

• Multiple configurations – see “Available Configura-

tions” table

The CY2304 has two banks of two outputs each.

• Multiple low-skew outputs

The CY2304 PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

25 µA of current draw.

— Output-output skew less than 200 ps

— Device-device skew less than 500 ps

• 10-MHz to 133-MHz operating range

• Low jitter, less than 200 ps cycle-cycle

• Space-saving 8-pin 150-mil SOIC package

• 3.3V operation

Multiple CY2304 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 500 ps.

The CY2304 is available in two different configurations, as

shown in the “Available Configurations” table. The CY2304–1

is the base part, where the output frequencies equal the

reference if there is no counter in the feedback path.

• Industrial temperature available

Functional Description

The CY2304 is a 3.3V zero delay buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom, and

other high-performance applications.

The CY2304–2 allows the user to obtain Ref and 1/2x or 2x

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the

feedback pin.

Pin Configuration

Logic Block Diagram

FBK

8-pin SOIC

Top View

CLKA1

FBK

REF

PLL

REF

CLKA1

CLKA2

GND

CLKB2

CLKB1

CLKA2

Extra Divider (-2)

CLKB1

CLKB2

Available Configurations

Device

FBK from

Bank A Frequency Bank B Frequency

CY2304-1

CY2304-2

Bank A or B

Bank A

Reference

Reference/2

Reference

Bank B

2 × Reference

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07247 Rev. *C

Revised December 7, 2002

12 3 4 5 6 7 8

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