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CY2304_11

更新时间: 2024-09-16 09:41:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 446K
描述
3.3 V Zero Delay Buffer

CY2304_11 数据手册

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CY2304  
3.3 V Zero Delay Buffer  
3.3  
V Zero Delay Buffer  
one of the outputs. The input-to-output skew is guaranteed to be  
less than 250 ps, and output-to-output skew is guaranteed to be  
less than 200 ps.  
Features  
Zero input-output propagation delay, adjustable by capacitive  
load on FBK input  
The CY2304 has two banks of two outputs each.  
Multiple configurations  
The CY2304 PLL enters a power down state when there are no  
rising edges on the REF input. In this mode, all outputs are  
three-stated and the PLL is turned off, resulting in less than  
25 A of current draw.  
Multiple low-skew outputs  
10 MHz to 133 MHz operating range  
90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz  
Space-saving 8-pin 150-mil SOIC package  
3.3 V operation  
Multiple CY2304 devices can accept the same input clock and  
distribute it in a system. In this case, the skew between the  
outputs of two devices is guaranteed to be less than 500 ps.  
The CY2304 is available in two different configurations, as  
shown in Table 1. The CY2304–1 is the base part, where the  
output frequencies equal the reference if there is no counter in  
the feedback path.  
Industrial temperature available  
Functional Description  
The CY2304–2 allows the user to obtain Ref and 1/2x or 2x  
frequencies on each output bank. The exact configuration and  
output frequencies depends on which output drives the feedback  
pin.  
The CY2304 is a 3.3 V zero delay buffer designed to distribute  
high-speed clocks in PC, workstation, datacom, telecom, and  
other high performance applications.  
The part has an on-chip phase-locked loop (PLL) that locks to an  
input clock presented on the REF pin. The PLL feedback is  
required to be driven into the FBK pin, and can be obtained from  
Logic Block Diagram  
FBK  
CLKA1  
PLL  
REF  
CLKA2  
/2  
Extra Divider (-2)  
CLKB1  
CLKB2  
Table 1. Available Configurations  
Device  
FBK from  
Bank A or B  
Bank A  
Bank A Frequency  
Reference  
Bank B Frequency  
CY2304-1  
CY2304-2  
CY2304-2  
Reference  
Reference/2  
Reference  
Reference  
Bank B  
2 × Reference  
Cypress Semiconductor Corporation  
Document Number: 38-07247 Rev. *I  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 4, 2011  
[+] Feedback  

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