CY2303SXIT

更新时间： 2024-01-21 23:34:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
7页	128K
描述
Phase-Aligned Clock Multiplier

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CY2303SXIT 数据手册

CY2303

Phase-Aligned Clock Multiplier

Features

Functional Description

• 3-multiplier configuration (1x, 2x, 4x Ref)

The CY2303 is a 3 output 3.3V phase-aligned system clock

designed to distribute high-speed clocks in PC, workstation,

datacom, telecom, and other high-performance applications.

• 10 MHz to 166.67 MHz operating range (reference input

from 10 MHz to 41.67 MHz)

The part allows user to obtain 1x, 2x, and 4x Ref output

• Phase Alignment

• 80 ps typical period jitter

• Output enable pin

• 3.3V operation

• 5V Tolerant input

frequencies on respective output pins.

The CY2303 has an on-chip PLL, which locks to an input clock

presented on the REFIN pin. The PLL feedback is internally

connected to the REF output. The input-to-output skew is

guaranteed to be less than ±200 ps, and output-to-output skew

is guaranteed to be less than 200 ps.

Multiple CY2303 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 400 ps.

• 8-pin 150-mil SOIC package

• Commercial and Industrial Temperature available

The CY2303 is available in commercial and industrial temper-

ature ranges.

Selector Guide

Part Number

Outputs

Input Frequency Range

Output Frequency Range

Specifics

CY2303SC,

10 MHz–41.67 MHz

10 MHz–166.67 MHz

Commercial Temperature

CY2303SXC

CY2303SI,

CY2303SXI

10 MHz–41.67 MHz

10 MHz–166.67 MHz

Industrial Temperature

Block Diagram

Pin Configuration

8-pin SOIC

Top View

FBK

REFx4

REFx2

REF

GND

REFIN

N/C

REF

PLL

REFIN

REFx2

REFx4

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07249 Rev. *B

Revised August 2, 2005

12 3 4 5 6 7

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