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CY23020LFI-3T PDF预览

CY23020LFI-3T

更新时间: 2024-02-24 06:28:28
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路
页数 文件大小 规格书
9页 112K
描述
10-output, 400-MHz LVPECL Zero Delay Buffer

CY23020LFI-3T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:7 X 7 MM, QFN-48针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.85系列:23020
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N48
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:9最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:400 MHzBase Number Matches:1

CY23020LFI-3T 数据手册

 浏览型号CY23020LFI-3T的Datasheet PDF文件第2页浏览型号CY23020LFI-3T的Datasheet PDF文件第3页浏览型号CY23020LFI-3T的Datasheet PDF文件第4页浏览型号CY23020LFI-3T的Datasheet PDF文件第5页浏览型号CY23020LFI-3T的Datasheet PDF文件第6页浏览型号CY23020LFI-3T的Datasheet PDF文件第7页 
CY23020-3  
10-output, 400-MHz LVPECL Zero Delay Buffer  
Features  
Overview  
• 400-ps max Total Timing Budget(TTB) window  
• 10 LVPECL outputs  
• 1 LVPECL differential input  
• Selectable output frequency range from 100 to 400 MHz  
• Multiply by 2 option  
• 15-ps RMS Cycle-Cycle Jitter  
• Power-down mode  
• Lock indicator  
TheCY23020-3 is a high-performance 400-MHz LVPECL  
Output phase-locked loop (PLL)-based zero delay buffer  
(ZDB) designed for high- speed clock distribution applications.  
The device features a guaranteed TTB window specifying all  
occurrences of output clocks with respect to the input  
reference clock across variations in voltage, temperature,  
process, frequency, and ramp rate.  
Additionally, the CY23020-3 can be used as a fan-out buffer  
via the S[1:2] control pins. In this mode, the PLL is bypassed  
and the reference clock is routed to the output buffers.  
• 3.3V power supply  
• Available in 48-pin QFN package  
Block Diagram  
Pin Configurations  
48  
47  
46  
45  
44  
43  
42  
41  
G
N
D
C
40  
38  
39  
R
E
F
37  
Q
9
V
D
D
C
R
E
F
-
V
D
D
L
F
B
O
U
T
+
F
B
I
N
-
F
B
I
N
+
N
C
V
D
D
O
C
K
LOCK  
+
FBOUT+  
+
FBOUT-  
Q9-  
36  
35  
34  
33  
1
FBOUT-  
1/  
2
÷ ÷  
REF+  
REF-  
FBIN+  
FBIN-  
Q1+  
Q1-  
GND  
Q8-  
2
3
4
5
6
GND  
Q1-  
PLL  
1
2
÷
Q2+  
Q2-  
÷
Q8+  
Q1+  
VDD  
Q2+  
Q3+  
Q3-  
VDD 32  
Q4+  
Q4-  
CY23020-3  
31  
Q7+  
Q7-  
S1:2  
RANGE  
MUL  
Q5+  
Q4-  
Control  
Logic  
30  
29  
28  
27  
26  
Q2-  
GND  
Q3-  
7
8
9
Q6+  
Q6-  
GND  
Q7+  
Q7-  
Q6-  
Q8+  
Q8-  
Q6+  
10 Q3+  
Q9+  
Q9-  
VDD  
11  
12  
VDD  
Q4+  
G
N
D
C
G
N
D
Q
5
-
R
A
N
G
E
G
N
D
C
V
D
D
C
S
2
S
1
M
U
L
V
D
D
C
Q
4
-
G
N
D
Q5+ 25  
13  
14  
15  
19  
20  
23  
16  
17  
18  
21  
24  
22  
Cypress Semiconductor Corporation  
Document #: 38-07473 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised June 5, 2003  

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