CY23020LFI-3T

更新时间： 2024-02-26 03:01:40

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟驱动器逻辑集成电路
页数	文件大小	规格书
9页	112K
描述
10-output, 400-MHz LVPECL Zero Delay Buffer

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CY23020LFI-3T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	7 X 7 MM, QFN-48	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.85	系列：	23020
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e0	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	48
实输出次数：	9	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC48,.27SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	240
电源：	3.3 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.15 ns	座面最大高度：	1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	7 mm
最小 fmax：	400 MHz	Base Number Matches：	1

CY23020LFI-3T 数据手册

CY23020-3

Inserting Other Devices in Feedback Path

Table 2. Frequency Range Setting

RANGE

Output Frequency Range

Due to the fact that the device has an external feedback path

the user has a wide range of control over its output to input

skewing effect. One of these is to be able to synchronize the

outputs of an external clock that is resultant from any of the

output clocks. This implementation can be applied to any

device (ASIC, multiple output clock buffer/driver, etc.) which is

put into the feedback path.

100–200 MHz

200–400 MHz

Table 3. Frequency Multiplication Table

MUL

Output Frequency

Referring to Figure 1, if the traces between the ASIC/buffer

and the destination of the clock signal(s) (A) are equal in length

to the trace between the buffer and the FBIN pin (B), the

signals at the destination(s) device (C) will be driven high at

the same time the Reference clock provided to the ZDB goes

high. Synchronizing the other outputs of the ZDB to the outputs

from the ASIC/Buffer is more complex however, as any propa-

gation delay in the ASIC/Buffer must be accounted for.

= REF

= 2 * REF

How to Implement Zero Delay

Typically, ZDBs multiply (fan-out) single-clock signals quantity

while simultaneously reducing or mitigating the time delay

associated with passing the clock through a buffering device.

In many cases the output clock is adjusted, in phase, to occur

later or more often before the device’s input clock to

compensate for a design’s physical delay inadequacies. Most

commonly this is done using a simple PCB trace as a time

delay element. The longer the trace the earlier the output clock

edges occur with respect to the reference input clock edges.

There are constraints when inserting other devices. If the

devices contain PLLs or excessively long delay times they can

easily cause the overall clocking system to become unstable

as the components interact. For these designs it is advisable

to contact Cypress for applications support.

Reference

Signal

In this way such effects as undesired transit time of a clock

signal across a PCB can be compensated for.

Zero

Delay

Buffer

ASIC/

Buffer

Feedback

Input

Figure 1. Output Buffer in Feedback Path

Table 4. Absolute Maximum Ratings^[3]

Parameter

Description

Voltage on any V_DDpin with respect to GND

Voltage on any input pin with respect to GND

Storage Temperature

Rating

–0.5 to +5.0

–0.5 to V_DD+ 0.5

–65 to +150

–40 to 85

Unit

V_DD

V_IN

T_STG

T_A

°C

Operation Temperature (QFN)

T_J

Junction Temperature

135

[4]

Table 5. PECL DC Output Specification

V_CC= 3.135

V_CC= 3.3

V_CC= 3.465

Parameter Description

Conditions

Min.

Max.

Min.

Max.

Min.

Max.

2.6

2.165

2.765

V_OH

V_OL

1.835

2.435

1.3

–1.3

–2

1.135

–1.3

1.735

–0.7

1.9

1.465

–1.3

2.065

–0.7

V_OH(rel to V_CC

)

–2

–1.4

–2

–1.4

V_OL(rel to V_CC

)

These result in the following mid point values:^[4]

V_MID((V_{OH +}V_OL)/2)

1.485

–1.65

2.085

–1.05

1.65

2.25

1.815

–1.65

2.415

–1.05

–1.65

–1.05

V_MIDRelative to V_CC

Notes:

3. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at

these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may

affect reliability.

4. The midpoint voltage is average value of a waveform. For differential signals the midpoint is assumed to be the same for both the true and complement since

the V_OHand V_OLof both the true and complement signals in general should be the same. V_MIDis not necessarily equal to the differential crossover voltage,

which may be skewed if there is differential time delays between the signals.

Document #: 38-07473 Rev. *A

Page 3 of 9

1 234 5 6 7...9

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CY23020ZC-1	CYPRESS	20-output, 200-MHz Zero Delay Buffer	获取价格
CY23020ZC-1	ROCHESTER	23020 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, 6 X	获取价格
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