Datasheet > CY2302_05

CY2302_05

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		倍频器
页数	文件大小	规格书
7页	85K
描述
Frequency Multiplier and Zero Delay Buffer

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CY2302_05 数据手册

CY2302

Frequency Multiplier and Zero Delay Buffer

Features

Table 1. Configuration Options

• 90ps typical jitter OUT2

FBIN

OUT1

OUT2

FS0

FS1

OUT1

2 X REF

4 X REF

REF

OUT2

REF

• 200ps typical jitter OUT1

• 65ps typical output-to-output skew

• 90ps typical propagation delay

• Voltage range: 3.3V±5%, or 5V±10%

• Output frequency range: 5MHz-133MHz

• Two outputs

2 X REF

REF/2

8 X REF

4 X REF

8 X REF

2 X REF

16 X REF

4 X REF

2 X REF

4 X REF

REF

• Configuration options allow various multiplications of

the reference frequency—refer to Table 1 to determine

the specific option which meets your multiplication

needs

8 X REF

• Available in 8-pin SOIC package

Block Diagram

Pin Configuration

SOIC

External feedback connection to

OUT1 or OUT2, not both

FBIN

OUT2

VDD

OUT1

FS1

GND

FS0

÷Q

FS1

Phase

Detector

Charge

Pump

Reference

Input

Loop

Filter

Output

Buffer

OUT1

OUT2

VCO

Output

Buffer

÷2

Cypress Semiconductor Corporation

Document #: 38-07154 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 29, 2005

12 3 4 5 6 7

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