Datasheet > CY2302_05

CY2302_05

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		倍频器
页数	文件大小	规格书
7页	85K
描述
Frequency Multiplier and Zero Delay Buffer

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数据手册

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CY2302_05 数据手册

CY2302

AC Electrical Characteristics: T_A= 0°C to +70°C or –40° to 85°C, V_DD= 3.3V ±5%^[3]

Parameter

f_IN

f_OUT

t_R

Description

Input Frequency^[1]

Output Frequency

Output Rise Time

Output Fall Time

Test Condition

Min.

Typ.

—

Max.

133

3.5

Unit

MHz

OUT1 15-pF load

—

0.8V to 2.0V, 15-pF load

2.0V to 0.8V, 15-pF load

—

t_F

—

2.5

t_ICLKR

Input Clock Rise

Time^[2]

—

t_ICLKF

t_D

t_LOCK

t_JC

Input Clock Fall Time^[2]

—

Duty Cycle

15-pF load^[5]

PLL Lock Time

Power supply stable

OUT1, f_OUT>30 MHz

OUT2, f_OUT>30 MHz

—

1.0

300

—

Jitter, Cycle-to-Cycle

—

200

—

t_DC

Die Out Time^[6]

100

—

Clock Cycles

t_SKEW

t_PD

Output-output Skew^[4]

Propagation Delay^[4]

250

350

–350

AC Electrical Characteristics: T_A= 0°C to +70°C or –40° to 85°C, V_DD= 5.0V ±10%^[3]

Parameter

f_IN

Description

Input Frequency^[1]

Output Frequency

Output Rise Time

Output Fall Time

Input Clock Rise Time^[2]

Input Clock Fall Time^[2]

Duty Cycle

Test Condition

Min.

Typ.

Max.

Unit

MHz

133

2.5

1.5

f_OUT

t_R

OUT1 15-pF load

—

0.8V to 2.0V, 15-pF load

2.0V to 0.8V, 15-pF load

t_F

—

t_ICLKR

t_ICLKF

t_D

—

15-pF load^{[5, 7]}

—

t_LOCK

t_JC

PLL Lock Time

Power supply stable

OUT1, f_OUT>30 MHz

OUT2, f_OUT>30 MHz

1.0

300

—

Jitter, Cycle-to-Cycle

—

200

—

t_DC

Die out time^[6]

100

clock

cycles

t_SKEW

t_PD

Output-output Skew^[4]

Propagation Delay^[4]

—

250

350

–350

Notes:

1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).

2. Longer input rise and fall time will degrade skew and jitter performance.

3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.

4. Skew is measured at 1.4V on rising edges.

5. Duty cycle is measured at 1.4V.

6. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to <16 MHz.

7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.

Document #: 38-07154 Rev. *A

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