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CY15B064J-SXE PDF预览

CY15B064J-SXE

更新时间: 2024-10-29 17:00:43
品牌 Logo 应用领域
英飞凌 - INFINEON 存储
页数 文件大小 规格书
19页 594K
描述
铁电存储器 (F-RAM)

CY15B064J-SXE 数据手册

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CY15B064J  
Figure 3. START and STOP Conditions  
SDA  
SCL  
SDA  
SCL  
S
P
STOP Condition  
START Condition  
Figure 4. Data Transfer on the I2C Bus  
handbook, full pagewidth  
P
S
SDA  
Acknowledgement  
signal from slave  
Acknowledgement  
signal from receiver  
MSB  
S
SCL  
S
1
1
2
7
8
9
ACK  
2
3
4 - 8  
9
or  
P
ACK  
START  
STOP or  
START  
Byte complete  
condition  
condition  
The receiver would fail to acknowledge for two distinct reasons.  
First is that a byte transfer fails. In this case, the no-acknowledge  
ceases the current operation so that the device can be  
addressed again. This allows the last byte to be recovered in the  
event of a communication error.  
Data/Address Transfer  
All data transfers (including addresses) take place while the SCL  
signal is HIGH. Except under the three conditions described  
above, the SDA signal should not change while SCL is HIGH.  
Acknowledge/No-acknowledge  
Second and most common, the receiver does not acknowledge  
to deliberately end an operation. For example, during a read  
operation, the CY15B064J will continue to place data onto the  
bus as long as the receiver sends acknowledges (and clocks).  
When a read operation is complete and no more data is needed,  
the receiver must not acknowledge the last byte. If the receiver  
acknowledges the last byte, this will cause the CY15B064J to  
attempt to drive the bus on the next clock while the master is  
sending a new command such as STOP.  
The acknowledge takes place after the 8th data bit has been  
transferred in any transaction. During this state the transmitter  
should release the SDA bus to allow the receiver to drive it. The  
receiver drives the SDA signal LOW to acknowledge receipt of  
the byte. If the receiver does not drive SDA LOW, the condition  
is a no-acknowledge and the operation is aborted.  
Figure 5. Acknowledge on the I2C Bus  
DATA OUTPUT  
BY MASTER  
No Acknowledge  
Acknowledge  
DATA OUTPUT  
BY SLAVE  
SCL FROM  
MASTER  
1
2
8
9
S
Clock pulse for  
START  
acknowledgement  
Condition  
Document Number: 002-10027 Rev. *C  
Page 5 of 18  

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