Datasheet > CY15B016Q-SXET

CY15B016Q-SXET

更新时间： 2024-10-29 17:00:39

品牌	Logo	应用领域
英飞凌 - INFINEON		存储
页数	文件大小	规格书
21页	853K
描述
铁电存储器 (F-RAM)

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中文翻译

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数据手册

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CY15B016Q-SXET 数据手册

CY15B016Q

The two SPI modes are shown in Figure 4 and Figure 5. The

status of the clock when the bus master is not transferring data is:

WREN - Set Write Enable Latch

The CY15B016Q will power up with writes disabled. The WREN

command must be issued before any write operation. Sending

the WREN opcode allows the user to issue subsequent opcodes

for write operations. These include writing the Status Register

(WRSR) and writing the memory (WRITE).

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

The device detects the SPI mode from the status of the SCK pin

when the device is selected by bringing the CS pin LOW. If the

SCK pin is LOW when the device is selected, SPI Mode 0 is

assumed and if the SCK pin is HIGH, it works in SPI Mode 3.

Sending the WREN opcode causes the internal Write Enable

Latch to be set. A flag bit in the Status Register, called WEL,

indicates the state of the latch. WEL = ‘1’ indicates that writes are

permitted. Attempting to write the WEL bit in the Status Register

has no effect on the state of this bit – only the WREN opcode can

set this bit. The WEL bit will be automatically cleared on the rising

edge of CS following a WRDI, a WRSR, or a WRITE operation.

This prevents further writes to the Status Register or the F-RAM

array without another WREN command. Figure 6 illustrates the

WREN command bus configuration.

Figure 4. SPI Mode 0

SCK

Figure 6. WREN Bus Configuration

MSB

LSB

SCK

Figure 5. SPI Mode 3

HI-Z

SCK

WRDI - Reset Write Enable Latch

The WRDI command disables all write activity by clearing the

Write Enable Latch. The user can verify that writes are disabled

by reading the WEL bit in the Status Register and verifying that

WEL is equal to ‘0’. Figure 7 illustrates the WRDI command bus

configuration.

MSB

LSB

Power Up to First Access

The CY15B016Q is not accessible for a t_PUtime after power up.

Users must comply with the timing parameter t_PU, which is the

minimum time from V_DD(min) to the first CS LOW.

Figure 7. WRDI Bus Configuration

Command Structure

There are six commands, called opcodes, that can be issued by

the bus master to the CY15B016Q. They are listed in Table 1.

These opcodes control the functions performed by the memory.

SCK

Table 1. Opcode commands

Name

WREN

Description

Set write enable latch

Write disable

Opcode

0000 0110b

0000 0100b

0000 0101b

0000 0001b

0000 0011b

0000 0010b

HI-Z

WRDI

RDSR

WRSR

READ

WRITE

Read Status Register

Write Status Register

Read memory data

Write memory data

Document Number: 002-10555 Rev. *C

Page 6 of 20

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中文翻译

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与CY15B016Q-SXET相关器件

型号	品牌	获取价格	描述	数据表
CY15B064J	CYPRESS	获取价格	64-Kbit (8K Ã 8) Serial (I2C) Automotive F-R
CY15B064J-SXA	INFINEON	获取价格	铁电存储器 (F-RAM)
CY15B064J-SXAT	INFINEON	获取价格	铁电存储器 (F-RAM)
CY15B064J-SXE	CYPRESS	获取价格	Memory Circuit, 8KX8, CMOS, PDSO8, SOIC-8
CY15B064J-SXE	INFINEON	获取价格	铁电存储器 (F-RAM)
CY15B064J-SXET	CYPRESS	获取价格	64-Kbit (8K Ã 8) Serial (I2C) Automotive F-R
CY15B064J-SXET	INFINEON	获取价格	铁电存储器 (F-RAM)
CY15B064Q	CYPRESS	获取价格	64-Kbit (8K Ã 8) Serial (SPI) Automotive F-R
CY15B064Q-SXA	INFINEON	获取价格	铁电存储器 (F-RAM)
CY15B064Q-SXAT	INFINEON	获取价格	铁电存储器 (F-RAM)

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