Datasheet > CY15B016Q-SXET

CY15B016Q-SXET

更新时间： 2024-04-09 18:58:34

品牌	Logo	应用领域
英飞凌 - INFINEON		存储
页数	文件大小	规格书
21页	853K
描述
铁电存储器 (F-RAM)

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY15B016Q-SXET 数据手册

CY15B016Q

the slave responds through the SO pin. Multiple slave devices

may share the SI and SO lines as described earlier.

these three bits are ‘don’t care’, Cypress recommends that these

bits be set to 0s to enable seamless transition to higher memory

densities.

The CY15B016Q has two separate pins for SI and SO, which can

be connected with the master as shown in Figure 2.

Serial Opcode

For a microcontroller that has no dedicated SPI bus, a

general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.

Figure 3 shows such a configuration, which uses only three pins.

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

CY15B016Q uses the standard opcodes for memory accesses.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

Status Register

CY15B016Q has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

The 16-Kbit serial F-RAM requires a 2-byte address for any read

or write operation. Because the address is only 11 bits, the first

five bits which are fed in are ignored by the device. Although

Figure 2. System Configuration with SPI port

SCK

MOSI

MISO

SCK

CY15B016Q

HOLD WP

SCK

CY15B016Q

HOLD WP

SI SO

SPI

Microcontroller

C S 1

H O LD 1

W P 1

C S 2

H O LD 2

W P 2

Figure 3. System Configuration without SPI port

P1.0

P1.1

SCK

CY15B016Q

HOLD WP

SI SO

Microcontroller

P1.2

For both these modes, the input data is latched in on the rising

SPI Modes

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

CY15B016Q may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

Document Number: 002-10555 Rev. *C

Page 5 of 20

1...3 4 567 8 9...21

下载PDF

与CY15B016Q-SXET相关器件

型号	品牌	描述	获取价格	数据表
CY15B064J	CYPRESS	64-Kbit (8K Ã 8) Serial (I2C) Automotive F-R	获取价格
CY15B064J-SXA	INFINEON	铁电存储器 (F-RAM)	获取价格
CY15B064J-SXAT	INFINEON	铁电存储器 (F-RAM)	获取价格
CY15B064J-SXE	CYPRESS	Memory Circuit, 8KX8, CMOS, PDSO8, SOIC-8	获取价格
CY15B064J-SXE	INFINEON	铁电存储器 (F-RAM)	获取价格
CY15B064J-SXET	CYPRESS	64-Kbit (8K Ã 8) Serial (I2C) Automotive F-R	获取价格