CXL5505M/P
CMOS-CCD 1H Delay Line for PAL
For the availability of this product, please contact the sales office.
Description
CXL5505M
14 pin SOP (Plastic)
CXL5505P
14 pin DIP (Plastic)
The CXL5505M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
Features
• Single 5V power supply
• Low power consumption 100mW (Typ.)
• Built-in peripheral circuits
• Built-in quadruple PLL circuit
Functions
• 1130-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
• PLL circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
°C
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
–10 to +60
–55 to +150 °C
CXL5505M
CXL5505P
400
800
mW
mW
Structure
CMOS-CCD
Recommended Operating Condition (Ta = 25°C)
Supply voltage 5 ± 5%
VDD
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
4.433619 MHz
• Input clock waveform Sine wave
• Clock frequency
fCLK
Input Signal Amplitude
VSIG 575mVp-p (Max.) (at internal clamp condition)
Blook Diagram and Pin Configuration (Top View)
13
9
14
12
11
10
8
Auto-bias circuit
PLL
Clock driver
Timing circuit
CCD
(1130bit)
Bias circuit (A)
Bias circuit (B)
Output circuit
(S/H 1bit)
Clamp circuit
1
2
3
4
5
6
7
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E90731B7X-PS