CXL5509M/P
CMOS-CCD 1H/2H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
CXL5509M
16 pin SOP (Plastic)
CXL5509P
16 pin DIP (Plastic)
The CXL5509M/P is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low-pass filter provide 1H
and 2H delay signals simultaneously (For NTSC
signals).
Features
• Single power supply (5V)
• Low power consumption 130mW (Typ.)
• Built-in peripheral circuits
• Built-in quadruple PLL circuit
• For NTSC signals
• 1 input and 2 outputs
(Outputs for both 1H and 2H delays)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
°C
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
–10 to +60
–55 to +150 °C
Functions
• 906-bit (1H) and 1816-bit (2H) CCD register
• Clock driver
CXL5509M
CXL5509P
400
800
mW
mW
• Auto-bias circuit
• Sync tip clamp circuit
• Sample-and-hold circuit
• Quadruple PLL circuit
Recommended Operating Condition (Ta = 25°C)
Supply voltage 5 ± 5%
VDD
V
Structure
CMOS-CCD
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
3.579545 MHz
• Input clock waveform sine wave
• Clock frequency
fCLK
Input Signal Amplitude
VSIG 571mVp-p (Max.) (at internal clamp condition)
Blook Diagram and Pin Configuration (Top View)
16
15
14
13
12
11
10
9
Auto-bias circuit
PLL
Driver
Timing circuit
CCD
(1816bit)
Clamp circuit
906bit
1816bit
Bias circuit
Output circuit
(S/H 1bit)
Output circuit
(S/H 1bit)
2
3
4
5
6
7
8
1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E91401B7X-PS