CXL5515M/P
CMOS-CCD 1H Delay Line for PAL
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Description
CXL5515M
CXL5515P
The CXL5515M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL chroma signals
including the external lowpass filter.
8 pin SOP (Plastic)
8 pin DIP (Plastic)
Features
• Single 5V power supply
• Low power consumption
• Built-in peripheral circuit
• Built-in tripling PLL circuit
• Center bias mode
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 575mVp-p (Max.)
Absolute Maximum Ratings (Ta = 25°C)
Functions
• 848-bit CCD register
• Clock driver
• Auto bias circuit
• Input center bias circuit
• Sample and hold circuit
• Tripling PLL circuit
• Inverted output
• Supply voltage
VDD
+6
V
°C
°C
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
–10 to +60
–55 to +150
CXL5515M 350
CXL5515P 480
mW
mW
Recommended Operating Range (Ta = 25˚C)
VDD 5V ± 5%
Structure
CMOS-CCD
Recommended Clock Conditions (Ta = 25˚C)
• Input clock amplitude
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)
• Clock frequency 4.433619MHz
• Input clock waveform Sine wave
fCLK
Block Diagram and Pin Configuration (Top View)
VDD
8
VCO OUT
7
VCO IN
6
CLK
5
PLL
Auto-bias circuit
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
Bias circuit
CCD
(848 bit)
Output circuit
(S/H 1 bit)
1
2
3
4
IN
AB
OUT
VSS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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