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CXL5515M/P PDF预览

CXL5515M/P

更新时间: 2024-01-12 15:23:38
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
9页 108K
描述
CMOS-CCD 1H Delay Line for PAL

CXL5515M/P 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP8,.3针数:8
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDIP-T8
长度:9.4 mm功能数量:1
端子数量:8最高工作温度:60 °C
最低工作温度:-10 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP8,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V认证状态:Not Qualified
座面最大高度:4.1 mm子类别:Other Consumer ICs
最大压摆率:20 mA最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

CXL5515M/P 数据手册

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CXL5515M/P  
CMOS-CCD 1H Delay Line for PAL  
For the availability of this product, please contact the sales office.  
Description  
CXL5515M  
CXL5515P  
The CXL5515M/P are CMOS-CCD delay line ICs  
designed for processing video signals. This ICs  
provide a 1H delay time for PAL chroma signals  
including the external lowpass filter.  
8 pin SOP (Plastic)  
8 pin DIP (Plastic)  
Features  
Single 5V power supply  
Low power consumption  
Built-in peripheral circuit  
Built-in tripling PLL circuit  
Center bias mode  
Input Signal Amplitude  
VSIG 500mVp-p (Typ.), 575mVp-p (Max.)  
Absolute Maximum Ratings (Ta = 25°C)  
Functions  
848-bit CCD register  
Clock driver  
Auto bias circuit  
Input center bias circuit  
Sample and hold circuit  
Tripling PLL circuit  
Inverted output  
Supply voltage  
VDD  
+6  
V
°C  
°C  
Operating temperature Topr  
Storage temperature Tstg  
Allowable power dissipation  
PD  
–10 to +60  
–55 to +150  
CXL5515M 350  
CXL5515P 480  
mW  
mW  
Recommended Operating Range (Ta = 25˚C)  
VDD 5V ± 5%  
Structure  
CMOS-CCD  
Recommended Clock Conditions (Ta = 25˚C)  
Input clock amplitude  
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)  
Clock frequency 4.433619MHz  
• Input clock waveform Sine wave  
fCLK  
Block Diagram and Pin Configuration (Top View)  
VDD  
8
VCO OUT  
7
VCO IN  
6
CLK  
5
PLL  
Auto-bias circuit  
Timing circuit  
Clock driver  
Bias circuit A  
Bias circuit B  
Bias circuit  
CCD  
(848 bit)  
Output circuit  
(S/H 1 bit)  
1
2
3
4
IN  
AB  
OUT  
VSS  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E94904-ST  

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