Datasheet > CXL5001M/P

CXL5001M/P

更新时间： 2024-09-22 23:44:43

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
8页	100K
描述
CMOS-CCD 1H Delay Line for NTSC

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CXL5001M/P 数据手册

CXL5001M/P

CMOS-CCD 1H Delay Line for NTSC

For the availability of this product, please contact the sales office.

Description

CXL5001M

8 pin SOP (Plastic)

CXL5001P

8 pin DIP (Plastic)

The CXL5001M/P are general-purpose CMOS-CCD

delay line ICs that provide 1H delay time for NTSC.

Features

• Low power consumtion 80mW (Typ.)

• Small size package (8-pin SOP, DIP)

• Low differential gain DG = 3% (Typ.)

• Input signal ampiitude 180 IRE (= 1.28Vp-p, Max.)

• Low input clock amplitude operation 150mVp-p (Min.)

• Built-in peripheral circuits (clock driver, timing

generator, autobias, and output circuits)

Functions

• 680-bit CCD register

• Clock drivers

• Autobias circuit

• Sync tip clamp circuit

• Sample and hold circuit

Structure

CMOS-CCD

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

VDD

VCL

• Supply voltage

• Operating temperature

• Storage temperature

Topr –10 to +60 °C

Tstg –55 to +150 °C

• Allowable power dissipation PD

CXL5001M 350 mW

CXL5001P 480 mW

Recommended Operating Conditions

Supply voltage

VDD

VCL

9 ± 5%

5 ± 5%

Recommended Clock Conditions

• Input clock amplitude

VCLK

fCLK

150mVp-p to 1.0Vp-p

(250mVp-p typ.)

10.7MHz

• Clock frequency

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E50799A78-PS

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与CXL5001M/P相关器件

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CXL5001P	SONY	获取价格	CMOS-CCD 1H Delay Line for NTSC
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CXL5003M	SONY	获取价格	CMOS-CCD 1H Delay Line for PAL
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CXL5005M	SONY	获取价格	CMOS-CCD 1H Delay Line for NTSC with PLL
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