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CXL5505M PDF预览

CXL5505M

更新时间: 2024-09-23 22:11:35
品牌 Logo 应用领域
索尼 - SONY 消费电路商用集成电路光电二极管
页数 文件大小 规格书
9页 127K
描述
CMOS-CCD 1H Delay Line for PAL

CXL5505M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:9.9 mm
功能数量:1端子数量:14
最高工作温度:60 °C最低工作温度:-10 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:2.25 mm子类别:Other Consumer ICs
最大压摆率:29 mA最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

CXL5505M 数据手册

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CXL5505M/P  
CMOS-CCD 1H Delay Line for PAL  
Description  
CXL5505M  
14 pin SOP (Plastic)  
CXL5505P  
14 pin DIP (Plastic)  
The CXL5505M/P are CMOS-CCD delay line ICs  
that provide 1H delay time for PAL signals including  
the external low-pass filter.  
Features  
Single 5V power supply  
Low power consumption 100mW (Typ.)  
Built-in peripheral circuits  
Built-in quadruple PLL circuit  
Functions  
1130-bit CCD register  
Clock driver  
Auto-bias circuit  
Input clamp circuit  
Sample-and-hold circuit  
PLL circuit  
Absolute Maximum Ratings (Ta = 25°C)  
Supply voltage  
VDD  
6
V
°C  
Operating temperature Topr  
Storage temperature Tstg  
Allowable power dissipation  
PD  
–10 to +60  
–55 to +150 °C  
CXL5505M  
CXL5505P  
400  
800  
mW  
mW  
Structure  
CMOS-CCD  
Recommended Operating Condition (Ta = 25°C)  
Supply voltage 5 ± 5%  
VDD  
V
Recommended Clock Conditions (Ta = 25°C)  
Input clock amplitude VCLK 0.3 to 1.0  
Vp-p  
(0.5Vp-p typ.)  
4.433619 MHz  
Input clock waveform Sine wave  
Clock frequency  
fCLK  
Input Signal Amplitude  
VSIG 575mVp-p (Max.) (at internal clamp condition)  
Blook Diagram and Pin Configuration (Top View)  
13  
9
14  
12  
11  
10  
8
Auto-bias circuit  
PLL  
Clock driver  
Timing circuit  
CCD  
(1130bit)  
Bias circuit (A)  
Bias circuit (B)  
Output circuit  
(S/H 1bit)  
Clamp circuit  
1
2
3
4
5
6
7
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E90731B7X-PS  

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