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CP3263,512

更新时间: 2024-09-13 14:41:31
品牌 Logo 应用领域
恩智浦 - NXP PC
页数 文件大小 规格书
55页 236K
描述
P89LPC930FDH

CP3263,512 技术参数

生命周期:Obsolete包装说明:4.40 MM, MO-153, SOT-361-1, PLASTIC, TSSOP-28
Reach Compliance Code:unknown风险等级:5.77
Base Number Matches:1

CP3263,512 数据手册

 浏览型号CP3263,512的Datasheet PDF文件第2页浏览型号CP3263,512的Datasheet PDF文件第3页浏览型号CP3263,512的Datasheet PDF文件第4页浏览型号CP3263,512的Datasheet PDF文件第5页浏览型号CP3263,512的Datasheet PDF文件第6页浏览型号CP3263,512的Datasheet PDF文件第7页 
P89LPC930/931  
8-bit microcontrollers with two-clock 80C51 core  
4 kB/8 kB 3 V Flash with 256-byte data RAM  
Rev. 05 — 15 December 2004  
Product data  
1. General description  
The P89LPC930/931 are single-chip microcontrollers designed for applications  
demanding high-integration, low cost solutions over a wide range of performance  
requirements. The P89LPC930/931 is based on a high performance processor  
architecture that executes instructions in two to four clocks, six times the rate of  
standard 80C51 devices. Many system-level functions have been incorporated into  
the P89LPC930/931 in order to reduce component count, board space, and system  
cost.  
2. Features  
A high performance 80C51 CPU provides instruction cycle times of 111 ns to  
222 ns for all instructions except multiply and divide when executing at 18 MHz.  
This is 6 times the performance of the standard 80C51 running at the same clock  
frequency. A lower clock frequency for the same performance results in power  
savings and reduced EMI.  
2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or  
driven to 5.5 V).  
4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.  
Byte-erase allowing code memory to be used for data storage.  
Flash program operation completes in 2 ms.  
Flash erase operation completes in 2 ms.  
256-byte RAM data memory.  
Two 16-bit counter/timers. Each timer may be configured to toggle a port output  
upon timer overflow or to become a PWM output.  
Real-Time clock that can also be used as a system timer.  
Two analog comparators with selectable inputs and reference source.  
Enhanced UART with fractional baud rate generator, break detect, framing error  
detection, automatic address detection and versatile interrupt capabilities.  
400 kHz byte-wide I2C-bus communication port.  
SPI communication port.  
Eight keypad interrupt inputs, plus two additional external interrupt inputs.  
Four interrupt priority levels.  
Watchdog timer with separate on-chip oscillator, requiring no external  
components. The Watchdog time-out time is selectable from 8 values.  
Active-LOW reset. On-chip power-on reset allows operation without external reset  
components. A reset counter and reset glitch suppression circuitry prevent  
spurious and incomplete resets. A software reset function is also available.  
 
 

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