Datasheet > CDP1822C

CDP1822C

更新时间： 2024-01-17 17:38:34

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
5页	30K
描述
High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM

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CDP1822C 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

CDP1822C 数据手册

CDP1822C/3

High-Reliability CMOS

256-Word x 4-Bit LSI Static RAM

March 1997

Features

Description

• For Applications in Aerospace, Military, and Critical

Industrial Equipment

The CDP1822C/3 is a 256 word by 4-bit random access

memory designed for use in memory systems where high

speed, low operating current, and simplicity in use are

desirable. The CDP1822 features high speed and excellent

noise immunity. It has separate data inputs and outputs and

utilizes a single power supply of 4V to 6.5V.

• Interfaces Directly with CDP1802 Microprocessor

• Very Low Operating Current

- At V

= 5V and Cycle Time = 1µs . . . . . . 4mA (Typ)

Two Chip Select inputs simplify system expansion. An output

Disable control provides Wire-OR-capability and is also

useful in common Input/Output systems. The Output Disable

input allows this RAM to be used in common data Input/Out-

put systems by forcing the output into a high impedance

state during a write operation independent of the Chip Select

input condition. The output assumes a high impedance state

when the Output Disable is at high level or when the chip is

deselected by CS1 and/or CS2.

• Static CMOS Silicon-On-Sapphire Circuitry

- CD4000 Series Compatible

• Industry Standard Pinout

• Two Chip Select Inputs - Simple Memory Expansion

• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)

Battery Voltage

• Single Power Supply Operation . . . . . . . . . . 4V to 6.5V

The high noise immunity of the CMOS technology is

preserved in this design. For TTL interfacing at 5V operation,

excellent system noise margin is preserved by using an

external pull-up resistor at each input.

• High Noise Immunity 30% of V . . . . . . . . . 4V to 6.5V

• Output Disable for Common I/O Systems

• Three-State Data Output for Bus Oriented Systems

• Separate Data Inputs and Outputs

• Latch-Up-Free Transient Radiation Tolerance

Ordering Information

PART

PACKAGE

SBDIP

TEMP. RANGE

NUMBER

PKG. NO.

-55 C to +125 C CDP1822CD3

D22.4A

Pinout

CDP1822C/3 (SBDIP)

OPERATIONAL MODES

INPUTS

TOP VIEW

CHIP

SELECT SELECT OUTPUT READ/

21 A4

DISABLE WRITE

MODE

Read

(CS1)

(CS2)

(OD)

(R/W)

OUTPUT

Read

R/W

CS1

O. D.

CS2

DO4

DI4

Write

Data In

Write

High

Impedance

Standby

High

Impedance

DI1

DO3

DI3

High

Impedance

DO1

DI2

DO2

Output

High

Disable

Impedance

Logic 1 = High, Logic 0 = Low, X = Don’t Care

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2981.1

6-19

12 3 4 5

中文翻译

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与CDP1822C相关器件

型号	品牌	获取价格	描述	数据表
CDP1822C3	INTERSIL	获取价格	High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM
CDP1822CD	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
CDP1822CD/3	ETC	获取价格	x4 SRAM
CDP1822CD3	RENESAS	获取价格	256X4 STANDARD SRAM, 500ns, CDIP22, SIDE BRAZED, DIP-22
CDP1822CDX	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
CDP1822CE	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
CDP1822CE	RENESAS	获取价格	256X4 STANDARD SRAM, 450ns, PDIP22
CDP1822CEX	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
CDP1822CEX	RENESAS	获取价格	256X4 STANDARD SRAM, 450ns, PDIP22, PLASTIC, DIP-22
CDP1822D	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM

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