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CDP1823C/3 PDF预览

CDP1823C/3

更新时间: 2024-11-06 02:59:07
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
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6页 31K
描述
High-Reliability CMOS 128-Word x 8-Bit Static RAM

CDP1823C/3 数据手册

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CDP1823C/3  
High-Reliability CMOS  
128-Word x 8-Bit Static RAM  
March 1997  
Features  
Description  
• For Applications in Aerospace, Military, and Critical  
Industrial Equipment  
The CDP1823C/3 is a 128 word x 8-bit CMOS/SOS static  
random access memory. It is compatible with the CDP1802,  
CDP1804, CDP1805, and CDP1806 microprocessors, and  
will interface directly without additional components. The  
CDP1823C has a recommended operating voltage range of  
4V to 6.5V.  
• Compatible with CDP1800-Series Microprocessors at  
Maximum Speed  
• Interfaces with CDP1800-Series Microprocessors  
without Additional Components  
The CDP1823C memory has 8 common data input and data  
output terminals for direct connection to a bidirectional data  
bus and is operated from a single voltage supply. Five chip  
select inputs are provided to simplify memory system  
expansion. In order to enable the CDP1823C, the chip select  
inputs CS2, CS3, and CS5 require a low input signal, and  
the chip select inputs CS1 and CS4 require a high input  
signal.  
• Fast Access Time  
o
• At V  
= 5V, +25 C . . . . . . . . . . . . . . . . . . . . . . . . 275ns  
DD  
• Single Voltage Supply  
• Common Data Inputs and Outputs  
• Multiple Chip Select Inputs to Simplify Memory  
System Expansion  
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V  
DD  
The MRD signal enables all 8 output drivers when in the low  
• Memory Retention for Standby Battery Voltage Down state and should be in a high state during a write cycle.  
o
to 2V at 25 C  
After valid data appear at the output, the address inputs may  
• Latch-Up-Free Transient Radiation Tolerance  
Ordering Information  
PART NUMBER  
be changed immediately. Output data will be valid until either  
the MRD signal goes high, the device is deselected, or t  
(access time) after address changes.  
AA  
PACKAGE TEMP. RANGE  
(5V)  
PKG. NO.  
o
o
SBDIP  
-55 C to +125 C CDP1823CD3  
D24.6  
Pinout  
CDP1823C/3  
(SBDIP)  
TOP VIEW  
BUS 0  
BUS 1  
BUS 2  
BUS 3  
BUS 4  
BUS 5  
BUS 6  
BUS 7  
CS1  
1
2
3
4
5
6
7
8
9
24  
V
DD  
23 A0  
22 A1  
21 A2  
20 A3  
19 A4  
18 A5  
17 A6  
16 MWR  
15 MRD  
14 CS5  
13 CS4  
CS2 10  
CS3 11  
V
12  
SS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2982.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
6-31  

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