CDP1824,
CDP1824C
March 1997
32-Word x 8-Bit Static RAM
Features
Description
• Fast Access Time
The CDP1824 and CDP1824C are 32-word x 8-bit fully static
CMOS random-access memories for use in CDP-1800
series microprocessor systems. These parts are compatible
with the CDP1802 microprocessor and will interface directly
without additional components.
- V
- V
= 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710ns
= 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320ns
DD
DD
• No Precharge or Clock Required
The CDP1824 is fully decoded and does not require a pre-
charge or clocking signal for proper operation. It has
common input and output and is operated from a single
voltage supply. The MRD signal (output disable control)
enables the three-state output drivers, and overrides the
MWR signal. A CS input is provided for memory expansion.
The CDP1824C is functionally identical to the CDP1824.
The CDP1824 has an operating range of 4V to 10.5V, and
the CDP1824C has an operating voltage range of 4V to
6.5V. The CDP1824 and CDP1824C are supplied in 18 lead
hermetic dual-in-line ceramic packages (D suffix), and in 18
lead dual-in-line plastic packages (E suffix).
Ordering Information
5V
10V
PACKAGE
TEMPERATURE RANGE
PKG. NO.
E18.3
o
o
CDP1824CE
CDP1824CEX
CDP1824CD
CDP1824E
PDIP
Burn-In
SBDIP
-40 C to +85 C
CDP1824EX
CDP1824D
E18.3
D18.3
o
o
-40 C to +85 C
Pinout
CDP1824, CDP1824C (PDIP, SBDIP)
TOP VIEW
OPERATIONAL MODES
FUNCTION
CS MRD MWR
DATA PINS STATUS
MA4
MA3
1
2
3
4
5
6
7
8
9
18 V
DD
READ
0
0
X
Output: High/LowDependent
on Data
17 MWR
16 MRD
15 CS
MA2
WRITE
0
1
1
0
Input: Output Disabled
MA1
Not
Selected
X
X
Output Disabled:
High-Impedance State
MA0
14 BUS 0
13 BUS 1
12 BUS 2
11 BUS 3
BUS 7
BUS 6
BUS 5
Standby
0
1
1
Output Disabled:
High-Impedance State
Logic 1 = High Logic 0 = Low X = Don’t Care
V
10
BUS 4
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1103.2
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