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CDP1822D PDF预览

CDP1822D

更新时间: 2024-02-22 07:21:04
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器内存集成电路
页数 文件大小 规格书
8页 44K
描述
256X4 STANDARD SRAM, 250ns, CDIP22

CDP1822D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:SIDE BRAZED, CERAMIC, DIP-22
针数:22Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.89Is Samacsys:N
最长访问时间:250 nsJESD-30 代码:R-CDIP-T22
JESD-609代码:e0内存密度:1024 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端口数量:1
端子数量:22字数:256 words
字数代码:256工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256X4输出特性:3-STATE
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP22,.4
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/10 V认证状态:Not Qualified
最大待机电流:0.0001 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.016 mA
最大供电电压 (Vsup):10.5 V最小供电电压 (Vsup):4 V
标称供电电压 (Vsup):10 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

CDP1822D 数据手册

 浏览型号CDP1822D的Datasheet PDF文件第2页浏览型号CDP1822D的Datasheet PDF文件第3页浏览型号CDP1822D的Datasheet PDF文件第4页浏览型号CDP1822D的Datasheet PDF文件第5页浏览型号CDP1822D的Datasheet PDF文件第6页浏览型号CDP1822D的Datasheet PDF文件第7页 
CDP1822,  
CDP1822C  
256-Word x 4-Bit  
LSI Static RAM  
March 1997  
Features  
Description  
• Low Operating Current  
- V = 5V, Cycle Time 1µs . . . . . . . . . . . . . . . . . . 8mA  
The CDP1822 and CDP1822C are 256-word by 4-bit static  
random-access memories designed for use in memory sys-  
tems where high speed, low operating current, and simplicity  
in use are desirable. The CDP1822 features high speed and  
a wide operating voltage range. Both types have separate  
data inputs and outputs and utilize single power supplies of  
4V to 6.5V for the CDP1822C and 4V to 10.5V for the  
CDP1822.  
DD  
• Industry Standard Pinout  
• Two Chip-Select Inputs-Simple Memory Expansion  
• Memory Retention for Standby Battery Voltage of 2V  
Minimum  
• Output-Disable for Common I/O Systems  
• Three-State Data Output for Bus-Oriented Systems  
• Separate Data Inputs and Outputs  
Two Chip-Select inputs are provided to simplify system  
expansion. An Output Disable control provides Wire-OR  
capability and is also useful in common Input/Output sys-  
tems. The Output Disable input allows these RAMs to be  
used in common data Input/Output systems by forcing the  
output into a high-impedance state during a write operation  
independent of the Chip-Select input condition. The output  
assumes a high-impedance state when the Output Disable is  
at high level or when the chip is deselected by CS1 and/or  
CS2.  
Ordering Information  
PKG.  
5V  
10V  
PACKAGE TEMP. RANGE  
NO.  
o
o
CDP1822CE  
CDP1822E  
PDIP  
-40 C to +85 C  
E22.4  
CDP1822CEX CDP1822EX  
CDP1822CD CDP1822D  
Burn-In  
SBDIP  
Burn-In  
E22.4  
The high noise immunity of the CMOS technology is pre-  
served in this design. For TTL interfacing at 5V operation,  
excellent system noise margin is preserved by using an  
external pull-up resistor at each input.  
o
o
-40 C to +85 C  
D22.4A  
D22.4A  
CDP1822CDX  
-
Pinout  
CDP1822, CDP1822C  
(PDIP, SBDIP)  
TOP VIEW  
OPERATIONAL MODES  
INPUTS  
CHIP  
SELECT SELECT OUTPUT READ/  
DISABLE WRITE  
CHIP  
A3  
A2  
A1  
A0  
A5  
A6  
A7  
1
2
22  
V
DD  
1
2
21 A4  
MODE  
Read  
(CS )  
1
(CS )  
2
(OD)  
(R/W)  
OUTPUT  
Read  
3
20 R/W  
0
0
0
1
1
1
0
0
1
1
0
0
4
19  
18  
17  
16  
15  
14  
13  
12  
CS1  
O. D.  
CS2  
DO4  
DI4  
Write  
Write  
Data In  
5
High  
Imped-  
ance  
6
7
8
V
Standby  
Standby  
1
X
X
X
0
X
X
1
X
X
X
High  
Imped-  
ance  
SS  
9
DI1  
DO3  
DI3  
10  
11  
DO1  
DI2  
High  
Imped-  
ance  
DO2  
Output  
X
High  
Disable  
Imped-  
ance  
NOTE:  
Logic 1 = High, Logic 0 = Low, X = Don’t Care.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 1074.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
6-11  

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