Datasheet > CDP1822E

CDP1822E

更新时间： 2024-11-05 22:48:47

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
8页	48K
描述
256-Word x 4-Bit LSI Static RAM

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中文翻译

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数据手册

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CDP1822E 数据手册

CDP1822,

CDP1822C

256-Word x 4-Bit

LSI Static RAM

March 1997

Features

Description

• Low Operating Current

- V = 5V, Cycle Time 1µs . . . . . . . . . . . . . . . . . . 8mA

The CDP1822 and CDP1822C are 256-word by 4-bit static

random-access memories designed for use in memory sys-

tems where high speed, low operating current, and simplicity

in use are desirable. The CDP1822 features high speed and

a wide operating voltage range. Both types have separate

data inputs and outputs and utilize single power supplies of

4V to 6.5V for the CDP1822C and 4V to 10.5V for the

CDP1822.

• Industry Standard Pinout

• Two Chip-Select Inputs-Simple Memory Expansion

• Memory Retention for Standby Battery Voltage of 2V

Minimum

• Output-Disable for Common I/O Systems

• Three-State Data Output for Bus-Oriented Systems

• Separate Data Inputs and Outputs

Two Chip-Select inputs are provided to simplify system

expansion. An Output Disable control provides Wire-OR

capability and is also useful in common Input/Output sys-

tems. The Output Disable input allows these RAMs to be

used in common data Input/Output systems by forcing the

output into a high-impedance state during a write operation

independent of the Chip-Select input condition. The output

assumes a high-impedance state when the Output Disable is

at high level or when the chip is deselected by CS1 and/or

CS2.

Ordering Information

PKG.

10V

PACKAGE TEMP. RANGE

NO.

CDP1822CE

CDP1822E

PDIP

-40 C to +85 C

E22.4

CDP1822CEX CDP1822EX

CDP1822CD CDP1822D

Burn-In

SBDIP

Burn-In

E22.4

The high noise immunity of the CMOS technology is pre-

served in this design. For TTL interfacing at 5V operation,

excellent system noise margin is preserved by using an

external pull-up resistor at each input.

-40 C to +85 C

D22.4A

CDP1822CDX

Pinout

CDP1822, CDP1822C

(PDIP, SBDIP)

TOP VIEW

OPERATIONAL MODES

INPUTS

CHIP

SELECT SELECT OUTPUT READ/

DISABLE WRITE

CHIP

21 A4

MODE

Read

(CS )

(OD)

(R/W)

OUTPUT

Read

20 R/W

CS1

O. D.

CS2

DO4

DI4

Write

Data In

High

Imped-

ance

Standby

High

Imped-

ance

DI1

DO3

DI3

DO1

DI2

High

Imped-

ance

DO2

Output

High

Disable

Imped-

ance

NOTE:

Logic 1 = High, Logic 0 = Low, X = Don’t Care.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 1074.2

6-11

12 3 4 5 6 7 8

中文翻译

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与CDP1822E相关器件

型号	品牌	获取价格	描述	数据表
CDP1822EX	INTERSIL	获取价格	256-Word x 4-Bit LSI Static RAM
CDP1822EX	RENESAS	获取价格	256X4 STANDARD SRAM, 250ns, PDIP22
CDP1823	INTERSIL	获取价格	128-Word x 8-Bit LSI Static RAM
CDP1823C	INTERSIL	获取价格	High-Reliability CMOS 128-Word x 8-Bit Static RAM
CDP1823C/3	INTERSIL	获取价格	High-Reliability CMOS 128-Word x 8-Bit Static RAM
CDP1823CD	INTERSIL	获取价格	128-Word x 8-Bit LSI Static RAM
CDP1823CD3	INTERSIL	获取价格	High-Reliability CMOS 128-Word x 8-Bit Static RAM
CDP1823CDX	INTERSIL	获取价格	128-Word x 8-Bit LSI Static RAM
CDP1823CE	INTERSIL	获取价格	128-Word x 8-Bit LSI Static RAM
CDP1823CEX	RENESAS	获取价格	IC,SRAM,128X8,CMOS,DIP,24PIN,PLASTIC

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