CD74HCT73

更新时间： 2024-11-22 23:04:31

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
8页	59K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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中文翻译

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数据手册

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CD74HCT73 数据手册

CD74HC73,

CD74HCT73

Data sheet acquired from Harris Semiconductor

SCHS134

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

February 1998

Features

Description

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

The Harris CD74HC73 and CD74HCT73 utilize silicon gate

CMOS technology to achieve operating speeds equivalent to

LSTTL parts. They exhibit the low power consumption of

standard CMOS integrated circuits, together with the ability

to drive 10 LSTTL loads.

[ /Title

(CD74

HC73,

CD74

HCT73

)

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

These ﬂip-ﬂops have independent J, K, Reset and Clock

inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Reset is

accomplished asynchronously by a low level input. This

device is functionally identical to the HC/HCT107 but differs

in terminal assignment and in some parametric limits.

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

/Sub-

ject

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

(Dual

J-K

Flip-

Flop

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 74HCT logic family is functionally as well as pin

compatible with the standard 74LS logic family.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Ordering Information

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

TEMP. RANGE

PKG.

NO.

PART NUMBER

CD74HC73E

CD74HCT73E

CD74HC73M

NOTES:

( C)

PACKAGE

14 Ld PDIP

14 Ld SOIC

-55 to 125

E14.3

• HC Types

- 2V to 6V Operation

E14.3

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

M14.15

at V

= 5V

• HCT Types

6. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

7. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Pinout

CD74HC73, CD74HCT73

(PDIP, SOIC)

TOP VIEW

1CP

14 1J

13 1Q

12 1Q

11 GND

10 2K

2CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1721.1

12 3 4 5 6 7 8

中文翻译

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与CD74HCT73相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT73E	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73EE4	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73EN	ETC	获取价格	Logic IC
CD74HCT73EX	RENESAS	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
CD74HCT73F	ETC	获取价格	Logic IC
CD74HCT73H	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,DIE
CD74HCT73M	ROCHESTER	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
CD74HCT73M	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,SOP,14PIN,PLASTIC
CD74HCT73M	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73M96	RENESAS	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14

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