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CD74HCT73MG4 PDF预览

CD74HCT73MG4

更新时间: 2024-11-23 04:01:15
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
15页 423K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

CD74HCT73MG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.67
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
湿度敏感等级:1位数:2
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):57 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:20 MHz

CD74HCT73MG4 数据手册

 浏览型号CD74HCT73MG4的Datasheet PDF文件第2页浏览型号CD74HCT73MG4的Datasheet PDF文件第3页浏览型号CD74HCT73MG4的Datasheet PDF文件第4页浏览型号CD74HCT73MG4的Datasheet PDF文件第5页浏览型号CD74HCT73MG4的Datasheet PDF文件第6页浏览型号CD74HCT73MG4的Datasheet PDF文件第7页 
CD54HC73, CD74HC73,  
CD74HCT73  
Data sheet acquired from Harris Semiconductor  
SCHS134E  
Dual J-K Flip-Flop with Reset  
Negative-Edge Trigger  
February 1998 - Revised September 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The ’HC73 and CD74HCT73 utilize silicon gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC73,  
CD74  
HCT73  
)
• Asynchronous Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Reset and Clock  
inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Reset is  
accomplished asynchronously by a low level input. This  
device is functionally identical to the HC/HCT107 but differs  
in terminal assignment and in some parametric limits.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
/Sub-  
ject  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
(Dual  
J-K  
Flip-  
Flop  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible  
with the standard LS logic family.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
PART NUMBER  
CD54HC73F3A  
CD74HC73E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC73M  
at V  
= 5V  
CC  
CD74HC73MT  
CD74HC73M96  
CD74HCT73E  
CD74HCT73M  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC73 (CERDIP)  
CD74HC73, CD74HCT73 (PDIP, SOIC)  
TOP VIEW  
1CP  
1R  
1
2
3
4
5
6
7
14 1J  
13 1Q  
12 1Q  
11 GND  
10 2K  
1K  
V
CC  
2CP  
2R  
9
8
2Q  
2Q  
2J  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD74HCT73MG4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT73M TI

完全替代

Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73E TI

完全替代

Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73EE4 TI

完全替代

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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