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CD74HCT73E PDF预览

CD74HCT73E

更新时间: 2024-11-25 23:04:31
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器
页数 文件大小 规格书
8页 59K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

CD74HCT73E 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.25系列:HCT
JESD-30 代码:R-PDIP-T14JESD-609代码:e4
长度:19.3 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.006 A位数:2
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:48 ns传播延迟(tpd):57 ns
认证状态:Not Qualified施密特触发器:No
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:6.35 mm最小 fmax:20 MHz
Base Number Matches:1

CD74HCT73E 数据手册

 浏览型号CD74HCT73E的Datasheet PDF文件第2页浏览型号CD74HCT73E的Datasheet PDF文件第3页浏览型号CD74HCT73E的Datasheet PDF文件第4页浏览型号CD74HCT73E的Datasheet PDF文件第5页浏览型号CD74HCT73E的Datasheet PDF文件第6页浏览型号CD74HCT73E的Datasheet PDF文件第7页 
CD74HC73,  
CD74HCT73  
Data sheet acquired from Harris Semiconductor  
SCHS134  
Dual J-K Flip-Flop with Reset  
Negative-Edge Trigger  
February 1998  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The Harris CD74HC73 and CD74HCT73 utilize silicon gate  
CMOS technology to achieve operating speeds equivalent to  
LSTTL parts. They exhibit the low power consumption of  
standard CMOS integrated circuits, together with the ability  
to drive 10 LSTTL loads.  
[ /Title  
(CD74  
HC73,  
CD74  
HCT73  
)
• Asynchronous Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Reset and Clock  
inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Reset is  
accomplished asynchronously by a low level input. This  
device is functionally identical to the HC/HCT107 but differs  
in terminal assignment and in some parametric limits.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
/Sub-  
ject  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
(Dual  
J-K  
Flip-  
Flop  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 74HCT logic family is functionally as well as pin  
compatible with the standard 74LS logic family.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC73E  
CD74HCT73E  
CD74HC73M  
NOTES:  
( C)  
PACKAGE  
14 Ld PDIP  
14 Ld PDIP  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
E14.3  
• HC Types  
- 2V to 6V Operation  
E14.3  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
M14.15  
at V  
= 5V  
CC  
• HCT Types  
6. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
7. Wafer and die for this part number is available which meets all  
electrical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
Pinout  
CD74HC73, CD74HCT73  
(PDIP, SOIC)  
TOP VIEW  
1CP  
1R  
1
2
3
4
5
6
7
14 1J  
13 1Q  
12 1Q  
11 GND  
10 2K  
1K  
V
CC  
2CP  
2R  
9
8
2Q  
2Q  
2J  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1721.1  
Copyright © Harris Corporation 1998  
1

CD74HCT73E 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT73MG4 TI

完全替代

Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73M TI

完全替代

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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