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BUK108-50GL PDF预览

BUK108-50GL

更新时间: 2024-11-13 09:02:23
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
11页 131K
描述
PowerMOS transistor Logic level TOPFET

BUK108-50GL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SMALL OUTLINE, R-PSSO-G2针数:3
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.76其他特性:LOGIC LEVEL COMPATIBLE, ESD PROTECTED
外壳连接:DRAIN配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:50 V最大漏极电流 (Abs) (ID):13.5 A
最大漏极电流 (ID):13.5 A最大漏源导通电阻:0.125 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSSO-G2
元件数量:1端子数量:2
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):40 W最大脉冲漏极电流 (IDM):54 A
认证状态:Not Qualified子类别:FET General Purpose Powers
表面贴装:YES端子形式:GULL WING
端子位置:SINGLE晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

BUK108-50GL 数据手册

 浏览型号BUK108-50GL的Datasheet PDF文件第2页浏览型号BUK108-50GL的Datasheet PDF文件第3页浏览型号BUK108-50GL的Datasheet PDF文件第4页浏览型号BUK108-50GL的Datasheet PDF文件第5页浏览型号BUK108-50GL的Datasheet PDF文件第6页浏览型号BUK108-50GL的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
PowerMOS transistor  
Logic level TOPFET  
BUK108-50GL  
DESCRIPTION  
QUICK REFERENCE DATA  
Monolithic temperature and  
overload protected logic level power  
MOSFET in a 3 pin plastic surface  
mount envelope, intended as a  
general purpose switch for  
automotive systems and other  
applications.  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Continuous drain source voltage  
Continuous drain current  
50  
13.5  
40  
150  
125  
V
A
W
˚C  
m  
PD  
Tj  
Total power dissipation  
Continuous junction temperature  
Drain-source on-state resistance  
RDS(ON)  
VIS = 5 V  
APPLICATIONS  
General controller for driving  
lamps  
motors  
solenoids  
heaters  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Vertical power DMOS output  
stage  
Low on-state resistance  
Overload protection against  
over temperature  
Overload protection against  
short circuit load  
Latched overload protection  
reset by input  
DRAIN  
O/V  
CLAMP  
POWER  
INPUT  
MOSFET  
5 V logic compatible input level  
Control of power MOSFET  
and supply of overload  
protection circuits  
RIG  
LOGIC AND  
derived from input  
PROTECTION  
Low operating input current  
ESD protection on input pin  
Overvoltage clamping for turn  
off of inductive loads  
SOURCE  
Fig.1. Elements of the TOPFET.  
PINNING - SOT404  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
D
S
mb  
TOPFET  
input  
drain  
2
I
P
3
source  
2
mb drain  
1
3
June 1996  
1
Rev 1.000  

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