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BUK110-50DL PDF预览

BUK110-50DL

更新时间: 2024-09-24 22:37:19
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
10页 94K
描述
PowerMOS transistor Logic level TOPFET

BUK110-50DL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SMALL OUTLINE, R-PSSO-G2Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.91
其他特性:LOGIC LEVEL COMPATIBLE, ESD PROTECTED外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:50 V
最大漏极电流 (Abs) (ID):45 A最大漏极电流 (ID):45 A
最大漏源导通电阻:0.035 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PSSO-G2元件数量:1
端子数量:2工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL最大功率耗散 (Abs):125 W
最大脉冲漏极电流 (IDM):180 A认证状态:Not Qualified
子类别:FET General Purpose Powers表面贴装:YES
端子形式:GULL WING端子位置:SINGLE
晶体管应用:SWITCHING晶体管元件材料:SILICON

BUK110-50DL 数据手册

 浏览型号BUK110-50DL的Datasheet PDF文件第2页浏览型号BUK110-50DL的Datasheet PDF文件第3页浏览型号BUK110-50DL的Datasheet PDF文件第4页浏览型号BUK110-50DL的Datasheet PDF文件第5页浏览型号BUK110-50DL的Datasheet PDF文件第6页浏览型号BUK110-50DL的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
PowerMOS transistor  
Logic level TOPFET  
BUK110-50DL  
DESCRIPTION  
QUICK REFERENCE DATA  
Monolithic temperature and  
overload protected logic level power  
MOSFET in a 3 pin plastic surface  
mount envelope, intended as a  
general purpose switch for  
automotive systems and other  
applications.  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Continuous drain source voltage  
Continuous drain current  
50  
45  
125  
150  
35  
V
A
W
˚C  
m  
PD  
Tj  
Total power dissipation  
Continuous junction temperature  
Drain-source on-state resistance  
RDS(ON)  
APPLICATIONS  
IISL  
Input supply current  
VIS = 5 V  
650  
µA  
General controller for driving  
lamps  
motors  
solenoids  
heaters  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Vertical power DMOS output  
stage  
Low on-state resistance  
Overload protection against  
over temperature  
Overload protection against  
short circuit load  
Latched overload protection  
reset by input  
DRAIN  
O/V  
CLAMP  
POWER  
INPUT  
MOSFET  
5 V logic compatible input level  
Control of power MOSFET  
and supply of overload  
protection circuits  
RIG  
LOGIC AND  
derived from input  
PROTECTION  
Lower operating input current  
permits direct drive by  
micro-controller  
ESD protection on input pin  
Overvoltage clamping for turn  
off of inductive loads  
SOURCE  
Fig.1. Elements of the TOPFET.  
PINNING - SOT404  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
D
S
mb  
TOPFET  
input  
drain  
2
I
P
3
source  
2
mb drain  
1
3
June 1996  
1
Rev 1.000  

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