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BUK113-50DL PDF预览

BUK113-50DL

更新时间: 2024-09-25 09:02:23
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
6页 34K
描述
PowerMOS transistor Logic level TOPFET

BUK113-50DL 数据手册

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Philips Semiconductors  
Objective specification  
PowerMOS transistor  
Logic level TOPFET  
BUK113-50DL  
DESCRIPTION  
QUICK REFERENCE DATA  
Monolithic overload protected logic  
level power MOSFET in a surface  
mount plastic envelope, intended as  
a general purpose switch for  
automotive systems and other  
applications.  
SYMBOL  
PARAMETER  
MIN. MAX. UNIT  
VDS  
ID  
Continuous drain source voltage  
Drain current limiting  
Total power dissipation  
-
4
-
50  
8
V
A
PD  
4
W
APPLICATIONS  
Tj  
Continuous junction temperature  
Drain-source on-state resistance  
-
-
150  
200  
˚C  
General controller for driving  
lamps  
RDS(ON)  
m  
small motors  
solenoids  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Vertical power DMOS output  
stage  
Overload protected up to  
125˚C ambient  
DRAIN  
Overload protection by current  
limiting and overtemperature  
sensing  
O/V  
CLAMP  
Latched overload protection  
reset by input  
POWER  
INPUT  
MOSFET  
5 V logic compatible input level  
Control of power MOSFET  
and supply of overload  
protection circuits  
RIG  
LOGIC AND  
derived from input  
PROTECTION  
Low operating input current  
permits direct drive by  
micro-controller  
ESD protection on all pins  
Overvoltage clamping for turn  
off of inductive loads  
SOURCE  
Fig.1. Elements of the TOPFET.  
PINNING - SOT223  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
4
D
TOPFET  
input  
drain  
2
I
P
3
source  
4
drain (tab)  
S
2
3
1
January 1996  
1
Rev 1.000  

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