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SCES588B – AUGUST 2004 − REVISED MARCH 2005
D
D
Control Inputs V /V Levels Are
D
D
I/Os Are 4.6-V Tolerant
IH IL
Referenced to V
Voltage
CCA
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
Isolation Feature − If Either V
Input
CC
CC
Is at GND, All Outputs Are in the
High-Impedance State
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
ESD Protection Exceeds JESD 22
− 8000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
− 1000-V Charged-Device Model (C101)
D
I
Supports Partial-Power-Down Mode
off
Operation
description/ordering information
This 24-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVCH24T245 is optimized to operate with V
as low as 1.2 V. The A port is designed to track V
/V
set at 1.4 V to 3.6 V. It is operational with V
accepts any supply voltage from 1.2 V to 3.6 V. The
/V
CCA CCB
CCA CCB
. V
CCA CCA
B port is designed to track V
. V
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
CCB CCB
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH24T245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCH24T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 5DIR, 6DIR, 1OE, 2OE,
3OE, 4OE, 5OE, and 6OE) are supplied by V
.
CCA
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
The V
state.
isolation feature ensures that if either V
input is at GND, then both ports are in the high-impedance
CC
CC
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CCA
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
LFBGA − GRG
LFBGA − ZRG (Pb-free)
74AVCH24T245GRGR
74AVCH24T245ZRGR
−40°C to 85°C
Tape and reel
WL245
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005, Texas Instruments Incorporated
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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
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