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ADuM4121BRIZ-RL PDF预览

ADuM4121BRIZ-RL

更新时间: 2024-09-21 00:50:31
品牌 Logo 应用领域
亚德诺 - ADI 驱动双极性晶体管光电二极管接口集成电路驱动器
页数 文件大小 规格书
16页 529K
描述
2 A peak output current (<2 Ω RDSON)

ADuM4121BRIZ-RL 数据手册

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Data Sheet  
ADuM4121/ADuM4121-1  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS  
Low-side voltages referenced to GND1. High side voltages referenced to GND2; 2.5 V ≤ VDD1 ≤ 6.5 V; 4.5 V ≤ VDD2 ≤ 35 V, TJ = −40°C to  
+125°C. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical  
specifications are at TJ = 25°C, VDD1 = 5.0 V, V DD2= 15 V.  
Table 1.  
Parameter  
Symbol  
Min  
4.5  
2.5  
−1  
Typ  
Max  
Unit  
Test Conditions/Comments  
DC SPECIFICATIONS  
High Side Power Supply  
VDD2 Input Voltage  
VDD2 Input Current, Quiescent  
Logic Supply  
VDD1 Input Voltage  
Input Current  
Logic Inputs (VI+, VI−)  
Input Current  
VDD2  
IDD2(Q)  
35  
2.7  
V
mA  
2.3  
VDD1  
IDD1  
6.5  
5
V
mA  
3.6  
VI+ = high, VI− = low  
II+, II−  
VIH  
0.01  
+1  
µA  
Input Voltage  
Logic High  
0.7 × VDD1  
3.5  
V
V
V
V
2.5 V ≤ VDD1 ≤ 5 V  
VDD1 > 5 V  
2.5 V ≤ VDD1 ≤ 5 V  
VDD1 > 5 V  
Logic Low  
VIL  
0.3 × VDD1  
1.5  
UVLO  
VDD1  
Positive-Going Threshold  
Negative-Going Threshold  
Hysteresis  
VVDD1UV+  
VVDD1UV−  
VVDD1UVH  
2.45  
2.35  
0.1  
2.5  
V
V
V
2.3  
VDD2  
Grade A  
Positive Going Threshold  
Negative Going Threshold  
Hysteresis  
VVDD2UV+  
VVDD2UV−  
VVDD2UVH  
4.4  
4.2  
0.2  
4.5  
V
V
V
4.1  
Grade B  
Positive Going Threshold  
Negative Going Threshold  
Hysteresis  
VVDD2UV+  
VVDD2UV−  
VVDD2UVH  
7.3  
7.1  
0.2  
7.5  
V
V
V
6.9  
Grade C  
Positive Going Threshold  
Negative Going Threshold  
Hysteresis  
VVDD2UV+  
VVDD2UV−  
VVDD2UVH  
11.3  
11.1  
0.2  
11.6  
V
V
V
10.8  
Thermal Shutdown (TSD)  
Positive Edge  
Hysteresis  
The ADuM4121-1 does not have TSD  
TTSD_POS  
TTSD_HYST  
RDSON_N  
155  
30  
°C  
°C  
Ω
Ω
Ω
Ω
Ω
V
Internal NMOS Gate Resistance  
0.6  
0.6  
0.8  
0.8  
0.8  
2
1.6  
1.6  
1.8  
1.8  
2
Tested at 250 mA, VDD2 = 15 V  
Tested at 1 A, VDD2 = 15 V  
Tested at 250 mA, VDD2 = 15 V  
Tested at 1 A, VDD2 = 15 V  
Tested at 200 mA, VDD2 = 15 V  
Referenced to GND2, VDD2 = 15 V  
VDD2 = 12 V, 4 Ω gate resistance  
Internal PMOS Gate Resistance  
RDSON_P  
Internal Miller Clamp Resistance  
Miller Clamp Voltage Threshold  
Peak Current  
RDSON_MILLER  
VCLP_TH  
IPK  
1.75  
50  
2.25  
2.3  
A
SWITCHING SPECIFICATIONS  
Pulse Width  
CL = 2 nF, VDD2 = 15 V, RGON1 = RGOFF1 = 5 Ω  
PW  
ns  
Propagation Delay  
Rising Edge2  
Falling Edge2  
tDLH  
tDHL  
22  
30  
32  
38  
42  
53  
ns  
ns  
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω  
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω  
Rev. 0 | Page 3 of 16  
 
 

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