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ADUM4135BRWZ-RL PDF预览

ADUM4135BRWZ-RL

更新时间： 2024-01-30 07:41:41
品牌 Logo 应用领域
亚德诺 - ADI 驱动光电二极管接口集成电路
页数 文件大小 规格书
17页 456K
描述
ADUM4135BRWZ-RL

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ADUM4135BRWZ-RL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Contact Manufacturer包装说明：SOP,
针数：16Reach Compliance Code：compliant
风险等级：5.73其他特性：SECONDARY SIDE SUPPLY (NEG SIDE)= -15V TO 0V
内置保护：TRANSIENT; THERMAL; UNDER VOLTAGE接口集成电路类型：BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.3 mm湿度敏感等级：3
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出电流流向：SOURCE AND SINK标称输出峰值电流：4.61 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260座面最大高度：2.65 mm
最大供电电压：6 V最小供电电压：2.3 V
标称供电电压：5 V电源电压1-最大：30 V
电源电压1-分钟：12 V电源电压1-Nom：15 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.5 mm
Base Number Matches：1

ADUM4135BRWZ-RL 数据手册

 浏览型号ADUM4135BRWZ-RL的Datasheet PDF文件第2页浏览型号ADUM4135BRWZ-RL的Datasheet PDF文件第3页浏览型号ADUM4135BRWZ-RL的Datasheet PDF文件第4页浏览型号ADUM4135BRWZ-RL的Datasheet PDF文件第5页浏览型号ADUM4135BRWZ-RL的Datasheet PDF文件第6页浏览型号ADUM4135BRWZ-RL的Datasheet PDF文件第7页 
Single-/Dual-Supply, High Voltage Isolated  
IGBT Gate Driver with Miller Clamp  
Data Sheet  
ADuM4135  
FEATURES  
GENERAL DESCRIPTION  
4 A peak drive output capability  
Output power device resistance: <1 Ω  
Desaturation protection  
Isolated desaturation fault reporting  
Soft shutdown on fault  
The ADuM4135 is a single-channel gate driver specifically  
optimized for driving insulated gate bipolar transistors  
(IGBTs). Analog Devices, Inc., iCoupler® technology provides  
isolation between the input signal and the output gate drive.  
The ADuM4135 includes a Miller clamp to provide robust  
IGBT turn-off with a single-rail supply when the gate voltage  
drops below 2 V (typical). Operation with unipolar or bipolar  
secondary supplies is possible, with or without the Miller clamp  
operation.  
Miller clamp output with gate sense input  
Isolated fault and ready functions  
Low propagation delay: 55 ns typical  
Minimum pulse width: 50 ns  
Operating temperature range: −40°C to +125°C  
Output voltage range to 30 V  
Input voltage range from 2.5 V to 6 V  
Output and input undervoltage lockout (UVLO)  
Creepage distance: 7.8 mm minimum  
The Analog Devices chip scale transformers also provide  
isolated communication of control information between the  
high voltage and low voltage domains of the chip. Information  
on the status of the chip can be read back from dedicated  
outputs. Control of resetting the device after a fault on the  
secondary is performed on the primary side of the device.  
100 kV/µs common-mode transient immunity (CMTI)  
20 year lifetime for 600 V rms or 1092 V dc working voltage  
Safety and regulatory approvals  
Integrated onto the ADuM4135 is a desaturation detection  
circuit that provides protection against high voltage short-  
circuit IGBT operation. The desaturation protection contains  
noise reducing features such as a 370 ns (typical) masking time  
after a switching event to mask voltage spikes due to initial  
turn-on. An internal 537 µA (typical) current source allows low  
device count and the internal blanking switch allows the  
addition of an external current source if more noise immunity  
is needed.  
5 kV ac for 1 minute per UL 1577  
CSA Component Acceptance Notice 5A  
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12  
V
IORM = 849 V peak (reinforced/basic)  
APPLICATIONS  
MOSFET/IGBT gate drivers  
PV inverters  
Motor drives  
Power supplies  
The secondary UVLO is set to 11.67 V (typical) with common  
IGBT threshold levels taken into consideration.  
FUNCTIONAL BLOCK DIAGRAM  
16  
V
1
SS2  
V
SS1  
V +  
2V  
TSD  
1
ADuM4135  
2
2
3
4
I
2
CLAMP  
LOGIC  
15 GATE_SENSE  
V –  
I
UVLO  
READY  
FAULT  
14  
13  
V
V
OUT_ON  
DD2  
MASTER  
LOGIC  
PRIMARY  
MASTER  
LOGIC  
SECONDARY  
2
ENCODE  
DECODE  
DECODE  
ENCODE  
1
1
5
12  
11  
V
OUT_OFF  
GND  
9V  
2
6
7
8
RESET  
2
V
DD1  
1
10  
9
DESAT  
V
SS1  
V
SS2  
1
UVLO  
2
NOTES  
1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE  
ISOLATED FROM EACH OTHER.  
Figure 1.  
Rev. D  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice.  
No license is granted by implication or otherwise under any patent or patent rights of Analog  
Devices. Trademarks and registeredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2015–2020 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 
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