Datasheet > 9ZX21901D

9ZX21901D

更新时间： 2023-12-20 18:45:08

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
19页	608K
描述
Enhanced DB1900Z Compliant 19-Output Buffer

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9ZX21901D 数据手册

9ZX21901D DATASHEET

Electrical Characteristics – Filtered Phase Jitter Parameters - PCIe Common Clocked

(CC) Architectures

Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions

INDUSTRY

PARAMETER

SYMBOL

CONDITIONS

PCIe Gen 1

MIN

TYP

MAX

UNITS

Notes

1,2,3

LIMIT

t_jphPCIeG1-CC

ps (p-p)

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

(rms)

0.4

0.8

1,2

t_jphPCIeG2-CC

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

(rms)

1.6

3.1

Phase Jitter,

PLL Mode

1.1

1,2

PCIe Gen 3

(rms)

0.40

t_jphPCIeG3-CC

0.28

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

PCIe Gen 4

(rms)

0.40

0.5

t_jphPCIeG4-CC

0.28

0.1

1,2

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

t_jphPCIeG1-CC

PCIe Gen 1

0.1

ps (p-p)

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

(rms)

0.1

1,2,4

t_jphPCIeG2-CC

Additive Phase Jitter,

Bypass mode

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

n/a

(rms)

0.105

0.13

PCIe Gen 3

(rms)

t_jphPCIeG3-CC

0.1

1,2,4

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

PCIe Gen 4

(rms)

t_jphPCIeG4-CC

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

¹Applies to all outputs,, when driven by 9SQL4958 or equivalent

²Based on PCIe Base Specification Rev4.0 version 0.7 draft. See http://www.pcisig.com for latest specifications.

³Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

⁴For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.

APRIL 17, 2018

19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI

1...6 7 8910 11 12...19

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