Datasheet > 9ZX21901D

9ZX21901D

更新时间： 2023-12-20 18:45:08

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
19页	608K
描述
Enhanced DB1900Z Compliant 19-Output Buffer

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9ZX21901D 数据手册

9ZX21901D DATASHEET

Electrical Characteristics – Skew and Differential Jitter Parameters

Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions

PARAMETER

CLK_IN, DIF[x:0]

SYMBOL

t_{SPO_PLL}

t_{PD_BYP}

CONDITIONS

MIN

-100

1.9

TYP

MAX UNITS NOTES

Input-to-Output Skew in PLL mode

at 100MHz, nominal temperature and voltage

Input-to-Output Skew in Bypass mode

at 100MHz, nominal temperature and voltage

Input-to-Output Skew Variation in PLL mode

at 100MHz, across voltage and temperature

Input-to-Output Skew Variation in Bypass

mode

100

1,2,4,5,8

1,2,3,5,8

2.6

0.0

t_{DSPO_PLL}

-50

CLK_IN, DIF[x:0]

t_{DSPO_BYP}

-250

0.0

250

1,2,3,5,8

at 100MHz, across voltage and temperature,

_AMB= T_COM

Output-to-Output Skew across all outputs,

common to PLL and Bypass mode, at 100MHz

DIF[x:0]

t_{SKEW_ALL}

1,2,3,8

PLL Jitter Peaking

PLL Bandwidth

Duty Cycle

j_peak-hibw

j_peak-lobw

pll_HIBW

pll_LOBW

t_DC

LOBW#_BYPASS_HIBW = 1

LOBW#_BYPASS_HIBW = 0

LOBW#_BYPASS_HIBW = 1

LOBW#_BYPASS_HIBW = 0

1.4

1.2

2.8

1.1

2.5

7,8

8,9

MHz

0.7

1.4

Measured differentially, PLL Mode

Measured differentially, Bypass Mode at

100MHz

Duty Cycle Distortion

t_DCD

-1

-0.5

1,10

PLL mode

1,11

Jitter, Cycle to Cycle

t_jcyc-cyc

Additive Jitter in Bypass Mode

0.1

Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.

Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.

All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.

⁴This parameter is deterministic for a given device.

Measured with scope averaging on to find mean value.

⁶t is the period of the input clock.

⁷Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.

Guaranteed by design and characterization, not 100% tested in production.

Measured at 3 db down or half power point.

¹⁰Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

¹¹Measured from differential waveform.

19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI

APRIL 17, 2018

1...5 6 789 10 11...19

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与9ZX21901D相关器件

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